US3786318A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having channel preventing structure
Assignee: Hitachi Ltd
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Filing: 1967-10-10
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Granted: 1974-01-15
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Expires: 1987-10-10
Abstract
Abstract A semiconductor device, wherein a plurality of light doped ptype silicon regions are formed separately in an island form on a heavily doped P type silicon substrate in contact therewith, semiconductor circuit elements like diodes, transistors, resistors, capacitors etc. are formed in the principal surfaces of the P regions and the exposed surface parts of the P substrate and P regions are covered with silicon oxide films. This invention provides a stabilized semiconductor device capable of high voltage operation, wherein the leakage current is small and the interaction between the circuits elements is small.
Inventors
- 👤 T Momoi
- 👤 I Homma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:08
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D99/00; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/20
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
189 words
An insulated gate type field effect transistor comprising a P type silicon substrate having a low resistivity; a P type silicon layer formed on said substrate and having a resistivity higher than that of said substrate; a source and a drain diffused region of N type formed in said P type layer; a ditch formed in said P type layer so as to completely surround said source and drain regions and extend to said substrate to expose the surface of said substrate; an insulating film having an inherent channel producing tendency covering the entire surface of said substrate exposed by said ditch and the surfaces of said P type layer and said source and drain regions; a source and a drain electrode ohmically connected to said source and drain regions through holes formed on said insulating film, respectively; and a gate electrode formed on said insulatIng film covering said substrate surface between said source and drain regions, wherein the resistivity of said P type silicon substrate is sufficiently low to prevent the conductivity type of the surface of said substrate under said insulating film from inverting to N type.
Claim 2
Dependent Claim
189 words
An insulated gate type field effect transistor comprising a P type silicon substrate having a low resistivity; a P type silicon layer formed on said substrate and having a resistivity higher than that of said substrate; a source and a drain diffused region of N type formed in said P type layer; a ditch formed in said P type layer so as to completely surround said source and drain regions and extend to said substrate to expose the surface of said substrate; an insulating film having an inherent channel producing tendency covering the entire surface of said substrate exposed by said ditch and the surfaces of said P type layer and said source and drain regions; a source and a drain electrode ohmically connected to said source and drain regions through holes formed on said insulating film, respectively; and a gate electrode formed on said insulatIng film covering said substrate surface between said source and drain regions, wherein the resistivity of said P type silicon substrate is sufficiently low to prevent the conductivity type of the surface of said substrate under said insulating film from inverting to N type.
Claim 3
Dependent Claim
27 words
An insulated gate field effect transistor according to claim 1, wherein the resistivity of the P type silicon substrate is not more than 0.1. Omega - cm.
Claim 4
Dependent Claim
27 words
An insulated gate field effect transitor according to claim 1, wherein the resistivity of the P type silicon substrate is not more than 0.01 Omega - cm.
Claim 5
Dependent Claim
29 words
An insulated gate field effect transistor according to claim 3, which further comprises a substrate electrode ohmically connected to the surface of said substrate opposing said P type layer.
References Cited (Backward Citations)
US3315096A
Cited
GB1015588A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |