Method for making Josephson junctions with contamination-free interfaces utilizing a ZnO contact insulator

Claim 1

A method of fabricating a Josephson junction integrated circuit device with contamination-free interfaces, comprising the steps of: providing a quartz substrate located in an ultra-high vacuum chamber; pumping said ultra-high vacuum chamber down to an ultra-high vacuum on the order of 1-5×10 -9 torr; depositing by RF sputtering onto said quartz substrate a 300 nm lower layer of NbN, said lower layer being deposited at 600°-700° C. under a partial pressure of Ar on the order of 11×10 -3 torr; depositing by RF sputtering at 300° C. a 4 nm layer of hydrogenated silicon onto said lower layer of NbN; oxidizing said layer of hydrogenated silicon in an oxygen atmosphere at 300° C.; depositing by RF sputtering onto said hydrogenated silicon layer a 20-50 nm upper layer of NbN, said upper layer being deposited under a partial pressure of Ar in the range of 20-30×10 -3 torr, all said depositing and oxidizing steps being done in said ultra-high vacuum chamber during a single pump-down thereof; sculpturing by anisotropic etching said deposited and oxidized layers to form base electrodes; anisotropically etching through said upper layer and said oxidized silicon layer to form pedestals of counter electrodes and barriers; depositing a 500 nm layer of ZnO over said device; etching via holes through said ZnO layer to the base and counter electrodes; depositing a 100 nm layer of a contact/lead superconducting material over said device, said contact/lead layer contacting said base and counter electrodes through said via holes in said ZnO layer; and etching said contact/lead layer to form a contact and lead pattern.

Claim 2

A method of fabricating a Josephson junction integrated circuit device with contamination-free interfaces, comprising the steps of: providing a quartz substrate located in an ultra-high vacuum chamber; pumping said ultra-high vacuum chamber down to an ultra-high vacuum on the order of 1-5×10 -9 torr; depositing by RF sputtering onto said quartz substrate a 300 nm lower layer of NbN, said lower layer being deposited at 600°-700° C. under a partial pressure of Ar on the order of 11×10 -3 torr; depositing by RF sputtering at 300° C. a 4 nm layer of hydrogenated silicon onto said lower layer of NbN; oxidizing said layer of hydrogenated silicon in an oxygen atmosphere at 300° C.; depositing by RF sputtering onto said hydrogenated silicon layer a 20-50 nm upper layer of NbN, said upper layer being deposited under a partial pressure of Ar in the range of 20-30×10 -3 torr, all said depositing and oxidizing steps being done in said ultra-high vacuum chamber during a single pump-down thereof; sculpturing by anisotropic etching said deposited and oxidized layers to form base electrodes; anisotropically etching through said upper layer and said oxidized silicon layer to form pedestals of counter electrodes and barriers; depositing a 500 nm layer of ZnO over said device; etching via holes through said ZnO layer to the base and counter electrodes; depositing a 100 nm layer of a contact/lead superconducting material over said device, said contact/lead layer contacting said base and counter electrodes through said via holes in said ZnO layer; and etching said contact/lead layer to form a contact and lead pattern.