Non-volatile dynamic RAM cell

Claim 2

A memory cell comprising: a storage capacitor having a storage node and a plate, means for applying a constant voltage to said plate, a control electrode, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider circuit being disposed between said control electrode and said storage node, a bit line, a switching device disposed between said storage node and said bit line, and a floating gate field effect transistor disposed between said storage node and said switching device and said floating gate field effect transistor being controlled by said floating gate.

Claim 3

A memory cell as set forth in claim 1 wherein said first capacitor includes a first enhanced conduction insulator.

Claim 4

A memory cell as set forth in claim 2 wherein said first capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 5

A memory cell as set forth in claim 3 wherein said switching device is a transistor.

Claim 6

A memory cell as set forth in claim 4 wherein said transistor is a field effect transistor.

Claim 7

A memory cell as set forth in claim 5 wherein said first capacitor is disposed between said floating gate and said control electrode and has a capacitance value substantially less than that of second capacitor.

Claim 8

A memory cell as set forth in claim 6 further including means for applying a voltage to said control electrode.

Claim 9

A memory cell as set forth in claim 7 wherein said means for applying a voltage to said control electrode applies a first voltage having a given magnitude during one period of time and a second voltage having a magnitude substantially lower than that of said given magnitude during another period of time.

Claim 10

A memory cell as set forth in claim 8 wherein said given insulating layer includes a silicon dioxide layer and each of said first and second enhanced conduction insulators includes a silicon-rich silicon dioxide layer.

Claim 11

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said storage node, wherein said first capacitor is disposed between said floating gate and said control electrode and has a capacitive value substantially less than that of said second capacitor, a bit line disposed in said substrate, a field effect transistor disposed between said storage node and said bit line, and a floating gate FET disposed between said storage node and said field effect transistor, said floating gate FET controlled by said floating gate.

Claim 12

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said storage node, wherein said first capacitor is disposed between said floating gate and said control electrode and has a capacitive value substantially less than that of said second capacitor, a bit line disposed in said substrate, a field effect transistor disposed between said storage node and said bit line, and a floating gate FET disposed between said storage node and said field effect transistor, said floating gate FET controlled by said floating gate.

Claim 13

A non-volatile dynamic random access memory cell as set forth in claim 10 wherein said first capacitor includes a first enhanced conduction insulator.

Claim 14

A non-volatile dynamic random access memory cell as set forth in claim 11 wherein said first capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 15

A non-volatile dynamic random access memory cell as set forth in claim 12 wherein said first capacitor includes a layer of silicon dioxide and first and second layers of silicon-rich silicon dioxide disposed on opposite sides of said layer of silicon dioxide.

Claim 16

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, a switching node, a switching device, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said switching node, a bit/sense line disposed in said substrate, a switching device between said storage node and said bit/sense line, and a floating gate FET disposed between said storage node and said switching device said floating gate FET being controlled by said floating gate.

Claim 17

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, a switching node, a switching device, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said switching node, a bit/sense line disposed in said substrate, a switching device between said storage node and said bit/sense line, and a floating gate FET disposed between said storage node and said switching device said floating gate FET being controlled by said floating gate.

Claim 18

A non-volatile dynamic random access memory cell as set forth in claim 14 wherein said first capacitor is disposed between said floating gate and said control electrode and has a capacitance value substantially less than that of said second capacitor.

Claim 19

A non-volatile dynamic random access memory cell as set forth in claim 15 wherein said first capacitor includes a first enhanced conduction insulator.

Claim 20

A memory cell as set forth in claim 16 wherein said first capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 21

A non-volatile dynamic random access memory cell as set forth in claim 17 wherein said first capacitor includes a layer of silicon dioxide and first and second layer of silicon-rich silicon dioxide disposed on opposite sides of said layer of silicon dioxide.

Claim 22

A memory cell comprising: a storage capacitor having a storage node and a plate, means for applying a constant voltage to said plate, a control electrode, a switching node, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider circuit being disposed between said control electrode and said switching node, a bit line, a switching device disposed between said switching node and said bit line, and a floating gate field effect transistor disposed between said storage node and said switching node and said floating gate field effect transistor being controlled by said floating gate.

Claim 23

A memory cell comprising: a storage capacitor having a storage node and a plate, means for applying a constant voltage to said plate, a control electrode, a switching node, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider circuit being disposed between said control electrode and said switching node, a bit line, a switching device disposed between said switching node and said bit line, and a floating gate field effect transistor disposed between said storage node and said switching node and said floating gate field effect transistor being controlled by said floating gate.

Claim 24

A memory cell as set forth in claim 19 wherein said second capacitor includes a first enhanced conduction insulator.

Claim 25

A memory cell as set forth in claim 20 wherein said second capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 26

A memory cell as set forth in claim 21 wherein said switching device is a transistor.

Claim 27

A memory cell as set forth in claim 22 wherein said transistor is a field effect transistor.

Claim 28

A memory cell as set forth in claim 23 wherein said second capacitor is disposed between said floating gate and said switching node and has a capacitance value substantially less than that of said first capacitor.

Claim 29

A memory cell as set forth in claim 24 further including means for applying a voltage to said control electrode.

Claim 30

A memory cell as set forth in claim 25 wherein said means for applying a voltage to said control electrode, applies a first voltage having a given magnitude during one period of time and a second voltage having a magnitude substantially lower than that of the given magnitude during another period of time.

Claim 31

A memory cell as set forth in claim 26 wherein said given insulating layer includes a silicon dioxide layer and each of said first and second enhanced conduction insulators includes a silicon-rich silicon dioxide layer.

Claim 32

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, a switching node, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said switching node, wherein said second capacitor is disposed between said floating gate and said switching node and has a capacitive value substantially less than that of said first capacitor, a bit line disposed in said substrate, a field effect transistor disposed between said switching node and said bit line, and a floating gate FET disposed between said storage node and said switching node, said floating gate FET controlled by said floating gate.

Claim 33

A non-volatile dynamic random access memory cell comprising: a semiconductor substrate, a storage capacitor having a plate and a storage node disposed in said substrate, a control electrode, a switching node, means for applying a voltage to said control electrode, said voltage having a first magnitude during one period of time and a second magnitude substantially smaller than said first magnitude during another period of time, a voltage divider circuit having serially-connected first and second capacitors and a floating gate connected to a common point between said first and second capacitors, said voltage divider being disposed between said control electrode and said switching node, wherein said second capacitor is disposed between said floating gate and said switching node and has a capacitive value substantially less than that of said first capacitor, a bit line disposed in said substrate, a field effect transistor disposed between said switching node and said bit line, and a floating gate FET disposed between said storage node and said switching node, said floating gate FET controlled by said floating gate.

Claim 34

A non-volatile dynamic random access memory cell as set forth in claim 28 wherein said second capacitor includes a first enhanced conduction insulator.

Claim 35

A non-volatile dynamic random access memory cell as set forth in claim 29 wherein said second capacitor further includes a second enhanced conduction insulator and a given insulating layer disposed between said first and second insulators.

Claim 36

A non-volatile dynamic random access memory cell as set forth in claim 30 wherein said second capacitor includes a layer of silicon dioxide and first and second layers of silicon-rich silicon dioxide disposed on opposite sides of said layer of silicon dioxide.