Structured logic array

Claim 2

A programmed logic array for processing binary input signals to produce binary output signals comprising: a first logic array having a plurality of input lines for receiving said binary input signals; a second logic array having a plurality of output lines on which said binary output signals emanate; a first plurality of wordlines, including CONDITION DETECTION wordlines, which emanate from said first array; a second plurality of wordlines, including THEN wordlines and an ELSE wordline, which enter into said second array; and combinatorial logic for receiving binary signals emanating from said first array on said first plurality of wordlines before said binary signals emanating from said first array enter said second array on said second plurality of wordlines, and for delivering to the ELSE wordline a signal of predetermined first binary level only if the signals on all the CONDITION DETECTION wordlines are of a predetermined second binary level so that said programmed logic array implements a CASE statement.

Claim 3

The programmed logic array of claim 1 wherein said plurality of input lines comprises a plurality of mutually exclusive groups, said first plurality of wordlines further includes a STATE DETECTION wordline, and said combinatorial logic is a logic device which delivers to the ELSE wordline the signal of the first binary level only if the signals on all the CONDITION DETECTION wordlines are of the predetermined second level while the signal on the STATE DETECTION wordline of the first plurality of wordlines is of a prescribed binary level, so that said programmed logic array implements a CASE statement for combinations of input signals present on at least one of said groups of input lines.

Claim 4

The programmed logic array of claim 1 wherein said plurality of input lines comprises first and second mutually exclusive groups, and said first plurality of wordlines further include a STATE DETECTION wordline, the second group's signals determining the signals on the CONDITION DETECTION wordlines, the first group's signals determining the signal on the STATE DETECTION wordline, and said combinatorial logic is a device which delivers to the ELSE wordline the signal of the first binary level if the signals on all the CONDITION DETECTION wordlines are of the second binary level while the signal on the STATE DETECTION wordline is of a prescribed level, whereby said programmed logic array implements a CASE statement for combinations of input signals present on said second group of input lines only when a preselected combination of input signals is present on said first group of input lines.

Claim 5

The programmed logic array of claim 1 wherein said plurality of input lines comprises first and second mutually exclusive groups, and said first plurality of wordlines further includes a STATE DETECTION wordline, the second group's signals determining the signals on the CONDITION DETECTION wordlines, the first group's signals determining the signal on the STATE DETECTION wordline of the first plurality of wordlines, and said combinatorial logic is a device which delivers to the ELSE wordline the signal of the first binary level if the signals on all the CONDITION DETECTION wordlines are of the second binary level while the signal on the STATE DETECTION wordline is of a prescribed level, whereby said programmed logic array implements a CASE statement for combinations of input signals present on said second group of input lines only when a preselected combination of input signals is not present on said first group of input lines.

Claim 6

A programmed logic array for processing binary inputs on two groups of input lines to produce binary outputs comprising: a DECODER array adapted to receive said binary inputs; a ROM array adapted from which said binary outputs emanate; a first plurality of DECODER wordlines which emanate from said DECODER array; a second plurality of ROM wordlines which enter said ROM array; and combinatorial logic connected to receive binary signals emanating from said DECODER array on said DECODER wordlines before said binary signals emanating from said DECODER array enter said ROM array on said ROM wordlines and to deliver on a preselected one of the second plurality of ROM wordlines a binary signal of prescribed level in response to the presence of a combination of said input signals comprising a first preselected combination on one group of input lines and one of a plurality of second preselected combinations on the other group of input lines.

Claim 7

A programmed logic array for processing binary inputs on two groups of input lines to produce binary outputs comprising: a DECODER array adapted to receive said binary inputs; a ROM array adapted from which said binary outputs emanate; a first plurality of DECODER wordlines which emanate from said DECODER array; a second plurality of ROM wordlines which enter said ROM array; and combinatorial logic connected to receive binary signals emanating from said DECODER array on said DECODER wordlines before said binary signals emanating from said DECODER array enter said ROM array on said ROM wordlines and to deliver on a preselected one of the second plurality of ROM wordlines a binary signal of prescribed level in response to the presence of a combination of said input signals comprising a first preselected combination on one group of input lines and one of a plurality of second preselected combinations on the other group of input lines.

Claim 8

A programmed logic array for processing binary input signals to produce binary output signals comprising: a first logic array adapted to receive said binary input signals; a second logic array from which said binary output signals emanate; a first plurality of wordlines which emanate from said first array, the binary signal on each of said first plurality of wordlines being responsive to a preselected combination of said binary input signals; a second plurality of wordlines which enter said second array; and multiple input combinatorial logic for receiving a multiplicity of binary signals emanating from said first array on said first plurality of wordlines before said signals emanating from said first array enter said second array on said second plurality of wordlines and for delivering binary signals to the second plurality of wordlines; the combinational logic being such that the signals delivered by said logic to first and second wordlines, respectively, of the second plurality is determined by the signals on both a first and a second wordline of the first plurality in accordance with differing first and second combinatorial logic functions, respectively.

Claim 9

A programmed logic array for processing binary input signals to produce binary output signals comprising: a first logic array adapted to receive said binary input signals; a second logic array from which said binary output signals emanate; a first plurality of wordlines which emanate from said first array, the binary signal on each of said first plurality of wordlines being responsive to a preselected combination of said binary input signals; a second plurality of wordlines which enter said second array; and multiple input combinatorial logic for receiving a multiplicity of binary signals emanating from said first array on said first plurality of wordlines before said signals emanating from said first array enter said second array on said second plurality of wordlines and for delivering binary signals to the second plurality of wordlines; the combinational logic being such that the signals delivered by said logic to first and second wordlines, respectively, of the second plurality is determined by the signals on both a first and a second wordline of the first plurality in accordance with differing first and second combinatorial logic functions, respectively.

Claim 10

Apparatus including a programmed logic array for processing binary input signals to produce binary output signals comprising: a first logic array having a plurality of input lines for receiving said binary input signals, said input lines comprising first and second mutually exclusive groups of input lines; a second logic array having a plurality of output lines on which the binary output signals emanate; a first plurality of intermediate wordlines which emanate from the first array; a second plurality of wordlines, operably connected to the first plurality of intermediate wordlines, which enter into the second array, said second plurality including a third plurality of THEN wordlines and an ELSE wordline; and a combinatorial logic element responsive to binary signals emanating from the first logic array on the first plurality of wordlines which delivers to the ELSE wordline a signal of a predetermined first level if and only if one of a first preselected set of combinations of input signals is not present on the first group of input lines when and only when any one of a second set of combinations of input signals is present on the second group of input lines.

Claim 11

Apparatus including a programmed logic array for processing binary input signals to produce binary output signals comprising: a first logic array having a plurality of input lines for receiving said binary input signals, said input lines comprising first and second mutually exclusive groups of input lines; a second logic array having a plurality of output lines on which the binary output signals emanate; a first plurality of intermediate wordlines which emanate from the first array; a second plurality of wordlines, operably connected to the first plurality of intermediate wordlines, which enter into the second array, said second plurality including a third plurality of THEN wordlines and an ELSE wordline; and a combinatorial logic element responsive to binary signals emanating from the first logic array on the first plurality of wordlines which delivers to the ELSE wordline a signal of a predetermined first level if and only if one of a first preselected set of combinations of input signals is not present on the first group of input lines when and only when any one of a second set of combinations of input signals is present on the second group of input lines.