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US4415818A
Expired / Lapsed
US
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Programmable sequential logic circuit devices
Assignee: NTT Inc
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Filing: 1980-01-07
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Granted: 1983-11-15
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Expires: 2000-01-07
Abstract
Abstract The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.
Inventors
- 👤 Katsuhiko Ogawa
- 👤 Shinju Horiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
259 words
A programmable sequential logic circuit device comprising: a first logic array for producing product terms of a first and second plurality of input signals; a second logic array having inputs coupled to said first logic array for producing sum terms of the outputs of said first logic array, said second logic array including output terminal means for manifesting sequential signals to an associated circuit; a two-dimensional array of flip-flop circuits having a plurality of rows of stages, each stage including a plurality of serially connected flip-flop circuits, said array of flip-flop circuits further including a first input terminal group connected to outputs of said second logic array for supplying sum term signals to the inputs of respective rows of stages, a second input terminal group connected to inputs of the respective stages other than said row inputs for receiving an external control signal for setting an internal state of the array of flip-flop circuits, and output terminals connected to said first logic array for supplying state signals thereto as said first plurality of input signals; and setting means connected to said second input terminal group for generating said external control signals for setting the initial internal state of said array of flip-flop circuits and for changing said internal state for permitting an interruption during the operation of said array of flip-flop circuits, whereby said device generates said sequential signals for said associated circuit in accordance with the second plurality of input signals applied to said first logic array and the present internal state of said array of flip-flop circuits.
Claim 2
Dependent Claim
259 words
A programmable sequential logic circuit device comprising: a first logic array for producing product terms of a first and second plurality of input signals; a second logic array having inputs coupled to said first logic array for producing sum terms of the outputs of said first logic array, said second logic array including output terminal means for manifesting sequential signals to an associated circuit; a two-dimensional array of flip-flop circuits having a plurality of rows of stages, each stage including a plurality of serially connected flip-flop circuits, said array of flip-flop circuits further including a first input terminal group connected to outputs of said second logic array for supplying sum term signals to the inputs of respective rows of stages, a second input terminal group connected to inputs of the respective stages other than said row inputs for receiving an external control signal for setting an internal state of the array of flip-flop circuits, and output terminals connected to said first logic array for supplying state signals thereto as said first plurality of input signals; and setting means connected to said second input terminal group for generating said external control signals for setting the initial internal state of said array of flip-flop circuits and for changing said internal state for permitting an interruption during the operation of said array of flip-flop circuits, whereby said device generates said sequential signals for said associated circuit in accordance with the second plurality of input signals applied to said first logic array and the present internal state of said array of flip-flop circuits.
Claim 3
Dependent Claim
152 words
The programmable sequential logic circuit device according to claim 1 wherein said first logic array comprises an AND gate array, said second logic array comprises an exclusive OR gate array having inputs connected to product term lines of said AND gate array, the outputs of respective stages of said array of flip-flop circuits representing the internal state of said flip-flop circuits are fed back in parallel to said AND gate array, and wherein said first logic array further comprises another AND gate array and said second logic array further comprises another exclusive OR gate array with its inputs connected to product term lines of said another AND gate array, said input signals are also applied to said another AND gate array and the outputs of said stages are also fed back to said another AND gate array, thereby producing an output to said associated circuit from said another exclusive OR gate array.
Claim 4
Dependent Claim
163 words
The programmable sequential logic circuit according to claim 1 wherein said first logic array comprises an AND gate array, said second logic circuit comprises an exclusive OR gate array having inputs connected to product term lines of said AND gate array the inputs of respective rows of said array of flip-flop circuits are connected to the outputs of said exclusive OR gate array, the outputs of respective stages representing the internal state of said circuit are fed back in parallel to said AND gate array, and wherein said first logic array further comprises another AND gate array and said second logic array further comprises an OR gate array with its inputs connected to product term lines of said another AND gate array, said input signals are applied to said another AND gate array through inverters, and the outputs of said stages are fed back to said another AND gate array, thereby producing an output to said associated circuit from said OR gate array.
Claim 5
Dependent Claim
114 words
The programmable sequential logic circuit device according to claim 1 wherein said first logic array comprises an AND gate array, said second logic array comprises an exclusive OR gate array with its inputs connected to product term lines of said AND gate array, the inputs of respective rows of said array of flip-flop circuits are connected to the outputs of a portion of said exclusive OR gate array, and the outputs of respective stages of said array of flip-flop circuits representing the internal state of said flip-flop circuits are fed back in parallel to said AND gate array whereby an output to said associated circuit is derived out from said exclusive OR gate array.
Claim 6
Dependent Claim
125 words
The programmable sequential logic circuit device according to claim 1 wherein said setting means includes memory means having input terminals characterized by receiving externally supplied state signals for said device and output terminals for manifesting said state signals, and logic means having input terminals coupled to said memory means output terminals and output terminals coupled to said second input terminal group of said array of flip-flop circuits for furnishing said externally supplied state signals stored in said memory means to said array of flip-flop circuits, whereby the internal state of said array of flip-flop circuits can be initially determined by the externally supplied state signals and also altered during sequential operation of said array of flip-flop circuits by receipt of said externally supplied state signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-14 | 1987-05-16 | 1987-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-14 | 1991-05-16 | 1991-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-14 | 1995-05-16 | 1995-11-15 | $7700.00 | Window Closed / Lapsed |