Patent US4403306A successfully refreshed from Google Patents.
US4403306A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory operable as static RAM or EAROM
Assignee: Toshiba Corp
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Filing: 1981-10-16
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Granted: 1983-09-06
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Expires: 2001-10-16
Abstract
Abstract A semiconductor memory comprises a CMOS flip-flop circuit and a pair of N-channel MNOS (Metal Nitride Oxide Semiconductor) transistors. A first MNOS transistor is connected between a first pair of CMOS transistors and a second MNOS transistor is connected between a second pair of CMOS transistors. The gates of the first and second MNOS transistors are connected to a control signal line. The control signal line is normally maintained at a reference voltage. When an erase pulse of first polarity is supplied to the control signal line, the first and second MNOS transistors are turned ON, so that the memory operates in the static RAM mode. When a write pulse of second polarity is supplied to the control signal line, the data stored in the static RAM mode becomes nonvolatile.
Inventors
- 👤 Kaoru Tokushige
- 👤 Masayoshi Nakane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:52
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
273 words
A semiconductor memory comprising: a first series circuit and a second series circuit which are connected in parallel across a power supply, said first series circuit having a first MOS transistor of P-channel type, a first diode which is poled in the forward direction with respect to the polarity of a power supply voltage, a first MNOS transistor of N-channel type and a second MOS transistor of N-channel type which are connected in series, said second series circuit having a third MOS transistor of P-channel type, a second diode which is poled in the forward direction with respect to the polarity of the power supply voltage, a second MNOS transistor of N-channel type and a fourth MOS transistor of N-channel type which are connected in series, a connection point between said first MNOS transistor and said second MOS transistor being connected to gates of said third and fourth MOS transistors and a connection point between said second MNOS transistor and said fourth MOS transistor being connected to gates of said first and second MOS transistors; first and second digit lines; a word selection line; a fifth MOS transistor of N-channel type connected between said first digit line and said connection point between said first MNOS transistor and said second MOS transistor and having its gate connected to said word selection line; a sixth MOS transistor of N-channel type connected between said second digit line and said connection point between said second MNOS transistor and said fourth MOS transitsor and having its gate connected to said word selection line; and a control signal line connected to gates of said first and second MNOS transistors.
Claim 2
Dependent Claim
273 words
A semiconductor memory comprising: a first series circuit and a second series circuit which are connected in parallel across a power supply, said first series circuit having a first MOS transistor of P-channel type, a first diode which is poled in the forward direction with respect to the polarity of a power supply voltage, a first MNOS transistor of N-channel type and a second MOS transistor of N-channel type which are connected in series, said second series circuit having a third MOS transistor of P-channel type, a second diode which is poled in the forward direction with respect to the polarity of the power supply voltage, a second MNOS transistor of N-channel type and a fourth MOS transistor of N-channel type which are connected in series, a connection point between said first MNOS transistor and said second MOS transistor being connected to gates of said third and fourth MOS transistors and a connection point between said second MNOS transistor and said fourth MOS transistor being connected to gates of said first and second MOS transistors; first and second digit lines; a word selection line; a fifth MOS transistor of N-channel type connected between said first digit line and said connection point between said first MNOS transistor and said second MOS transistor and having its gate connected to said word selection line; a sixth MOS transistor of N-channel type connected between said second digit line and said connection point between said second MNOS transistor and said fourth MOS transitsor and having its gate connected to said word selection line; and a control signal line connected to gates of said first and second MNOS transistors.
Claim 3
Dependent Claim
49 words
A semiconductor memory cell according to claim 1, wherein said control signal line is normally maintained at a reference voltage, and said memory cell is arranged to operate in a static RAM mode in response to application of an erase pulse of first polarity to said control signal line.
Claim 4
Dependent Claim
75 words
A semiconductor memory cell according to claim 1, wherein said control signal line is normally maintained at a reference voltage, and said memory cell is arranged to operate in a static RAM mode in response to application of an erase pulse of first polarity to said control signal line, and to make data stored in the RAM mode nonvolatile in response to application of a write pulse of second polarity to said control signal line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-05 | 1987-03-07 | 1987-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-05 | 1991-03-07 | 1991-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-05 | 1995-03-07 | 1995-09-06 | $7700.00 | Window Closed / Lapsed |