Integrated semiconductor memory array having improved logic latch circuitry

Claim 1

An integrated semiconductor memory array comprising in combination: (a) a plurality of latch circuits arranged in columns and rows, each latch circuit having a pair of branches, each branch comprising an IGFET driver and an IGFET load connected in series drain-to-drain at a common node, the control gate of the IGFET driver of each branch of a latch being connected to the node of the other branch of that latch, at least one IGFET of each latch having a variable threshold voltage; (b) means for normally maintaining a first voltage across the two branches of all of said latches which is below that required to change the thresholds of the variable threshold IGFETs of those branches; (c) means for applying an input signal to at least one node of each latch in a selected column so as to store information in said latch in volatile form; (d) means for selectively enabling all latches in a given row to receive said input signals so that, by means of the last two named means any one or more of said latches may be selected to receive information in volatile form, thereby achieving volatile storage of information in all of said selected latches; (e) means for temporarily raising the voltage across all of said branches a second, higher, level which is sufficient to cause a long term change in the thresholds of all of said variable threshold transistors, thereby achieving non-volatile storage of the volatile information in all of said latches; and (f) means for applying substantially identical voltages to both nodes of at least one selected latch, while maintaining said first voltage across all of said latches, for selectively obliterating the volatile information content of only said selected latch, resulting in said selected latch assuming the state dictated by the threshold state of its at least one variable threshold IGFET without disturbing the volatile information contents of non-selected latches.