Nonvolatile counter circuit

Claim 2

A nonvolatile counter circuit, comprising: a power supply; flip-flop circuit means for temporarily storing information coupled to said power supply; a nonvolatile insulated gate type field effect memory transistor coupled to said flip-flop circuit; a switching element coupled in parallel with said nonvolatile memory transistor; transferring means coupled to said power supply for sensing a first state of said power supply and for transferring information stored in said nonvolatile memory transistor to said flip-flop circuit means upon detecting said first state of said power supply; erasing means coupled to said nonvolatile memory transistor for erasing information stored therein; short circuiting means coupled to said switching element for rendering said switching element conductive and writing means coupled to said power supply for writing information stored in said flip-flop circuit means into said nonvolatile memory transistor upon detecting a second state of said power supply.

Claim 3

A nonvolatile counter circuit according to claim 1 wherein: said nonvolatile memory transistor is a MNOS transistor.

Claim 4

A nonvolatile counter circuit according to claim 1 wherein: said nonvolatile memory transistor is a MAOS transistor.

Claim 5

A nonvolatile counter circuit according to claim 1 wherein: said switching element is a field effect transistor.

Claim 6

A nonvolatile counter circuit according to claim 4 wherein: said field effect transistor is a MOS transistor.

Claim 7

A nonvolatile counter circuit according to claim 1 wherein said flip-flop circuit means comprises: a plurality of field effect transistors, each having source, drain and gate electrodes; a first load transistor having its drain connected to said power supply and having its source and gate electrodes coupled together; a first storage transistor having its drain connected to the source of said load transistor; a second load transistor having its drain connected to said power supply and having its source and gate electrodes coupled together; a second storage transistor having its drain connected to the source of said second load transistor; a fifth transistor having its drain connected to the source of said first storage transistor, having its source connected to ground and having its gate connected to the source of said second storage transistor; a sixth transistor having its drain connected to the source of said second storage transistor, having its source connected to ground and having its gate connected to the source of said first storage transistor; a first switching transistor connected in parallel with said first storage transistor; a second switching transistor connected in parallel with said second storage transistor; and wherein the gates of said first and second storage transistors being connected together for common application of a first control signal and the gates of said first and second switching transistors adapted to be fed by a second control signal.

Claim 8

A nonvolatile counter circuit as in claim 1, further comprising: a count input control circuit; a count clear circuit; and a carry circuit.

Claim 9

A nonvolatile counter circuit as in claim 7, wherein said count input control circuit includes: an inverter circuit, and first and second NOR circuits.

Claim 10

A nonvolatile counter circuit as in claim 8 wherein said count clear circuit includes: three interconnected NOR circuits.

Claim 11

A nonvolatile counter circuit as in claim 7, further comprising: a pulse generating circuit, said pulse generating circuit coupled to said power supply to said count input control circuit and to said count clear circuit, whereby all counting functions are prevented when said power supply is switching from said first state to said second state.

Claim 12

A nonvolatile counter circuit as in claim 1, wherein said switching element comprises: a field effect transistor coupled across the source and drain of said memory transistor whereby said switching element is adapted to short circuit said memory transistor.

Claim 13

A nonvolatile counter circuit as in claim 1, further comprising circuit means for inhibiting counting operations of said counter circuit during operation of said transferring means.

Claim 14

A nonvolatile counter circuit as in claim 1, further comprising: a second memory transistor coupled to said flip-flop circuit; and a second switching element coupled across said second memory transistor whereby said second switching element is adapted to short circuit said second memory transistor.