Semiconductor memory

Claim 2

A semiconductor memory comprising: a. at least one memory cell including 1. a pair of transistors each having a collector, a base and a single emitter, 2. means for connecting the collector of each transistor to the base of the other transistor, respectively, and 3. a pair of switched impedance elements connected, respectively, in the collector circuits of said pair of transistors, each of said switched impedance elements presenting a high or a low impedance value when an address voltage supplied thereto has a high or a low level, respectively; b. a pair of digit lines coupled to said memory cell, said respective digit lines being connected to the respective emitters of said pair of transistors; c. a collector bias source coupled to said memory cell for supplying a collector bias voltage to the collectors of said pair of transistors through said switched impedance elements, respectively; and d. address voltage supply means connected to said switched impedance elements for supplying to said switched impedance elements an address voltage of the high or low level when said memory cell is selected or non-selected, respectively, and for causing both said switched impedance elements to present said high impedance value when the address voltage supplied thereto has said high level, so that both the collector impedances viewed from the respective collectors into said switched impedance elements are concurrently provided at the low or the high value when the memory cell is selected or non-selected, thereby attaining high speed operation in said memory cell.

Claim 3

means for connecting the collector of each transistor to the base of the other transistor, respectively, and

Claim 4

means for connecting the collector of each transistor to the base of the other transistor, respectively, and

Claim 5

A semiconductor memory according to claim 1, wherein each said switched impedance element in each collector circuit comprises

Claim 6

a low value resistor having a low resistance value, and

Claim 7

a low value resistor having a low resistance value, and

Claim 8

a plurality of address lines, each of which is coupled commonly to the memory cells located in the same row of the matrix, respectively, and

Claim 9

a plurality of address lines, each of which is coupled commonly to the memory cells located in the same row of the matrix, respectively, and

Claim 10

address voltage supply means for applying to said respective switched impedance elements concurrently the address voltage having the first or the second level depending on whether said memory cell is to be selected or non-selected, respectively, whereby both said collector load impedance elements concurrently present the low impedance value or the high impedance value when the memory cell is selected or non-selected, respectively; and

Claim 11

address voltage supply means for applying to said respective switched impedance elements concurrently the address voltage having the first or the second level depending on whether said memory cell is to be selected or non-selected, respectively, whereby both said collector load impedance elements concurrently present the low impedance value or the high impedance value when the memory cell is selected or non-selected, respectively; and

Claim 12

a pair of collector load impedance elements connected at one end thereof to the collectors of said pair of transistors; b. a collector bias source connected to the other end of said collector load impedance elements for supplying to the respective collectors of said pair of transistors a collector bias voltage; c. a pair of digit lines connected to the respective emitters of said pair of transistors; d. an address line coupled to said memory cell for supplying to said memory cell an address voltage having a first level by which said memory cell is rendered into a selected state and a second level by which said memory cell is retained in a non-selected state; e. a signal read-out circuit connected with said digit lines for reading-out the stored contents in the memory cell when it is in the selected state; and f. a signal write-in circuit connected to each of said digit lines for writing-in information to be stored into the memory cell when it is in the selected state; the improvement which comprises

Claim 13

a pair of collector load impedance elements connected at one end thereof to the collectors of said pair of transistors; b. a collector bias source connected to the other end of said collector load impedance elements for supplying to the respective collectors of said pair of transistors a collector bias voltage; c. a pair of digit lines connected to the respective emitters of said pair of transistors; d. an address line coupled to said memory cell for supplying to said memory cell an address voltage having a first level by which said memory cell is rendered into a selected state and a second level by which said memory cell is retained in a non-selected state; e. a signal read-out circuit connected with said digit lines for reading-out the stored contents in the memory cell when it is in the selected state; and f. a signal write-in circuit connected to each of said digit lines for writing-in information to be stored into the memory cell when it is in the selected state; the improvement which comprises

Claim 14

load means connected in the collector circuit of each transistor, said load means including a high impedance load connected to the collector of each said transistor for providing high impedance collector loads for the transistors, and a switched impedance element in shunt with each of said high impedance collector loads for providing a low impedance path around each high impedance collector load when the switched impedance element is rendered conductive, by being supplied with the address voltage of the high level; b. source means for providing a collector voltage to the collectors of the respective pair transistors through the load means, respectively; and c. address means for providing the address voltage of the high or the low level to said switched impedance elements, so that both said switched impedance elements are rendered non-conductive when the address voltage applied thereto is at a low leveL and at least one of said switched impedance elements is rendered conductive when the address voltage applied thereto is at a high level.

Claim 15

load means connected in the collector circuit of each transistor, said load means including a high impedance load connected to the collector of each said transistor for providing high impedance collector loads for the transistors, and a switched impedance element in shunt with each of said high impedance collector loads for providing a low impedance path around each high impedance collector load when the switched impedance element is rendered conductive, by being supplied with the address voltage of the high level; b. source means for providing a collector voltage to the collectors of the respective pair transistors through the load means, respectively; and c. address means for providing the address voltage of the high or the low level to said switched impedance elements, so that both said switched impedance elements are rendered non-conductive when the address voltage applied thereto is at a low leveL and at least one of said switched impedance elements is rendered conductive when the address voltage applied thereto is at a high level.

Claim 16

signal write-in voltage supply means for applying to one of the pair of digit lines a write-in voltage having a higher level than its normal level under the non-selected state when a signal is to be written into the memory cell.

Claim 17

signal write-in voltage supply means for applying to one of the pair of digit lines a write-in voltage having a higher level than its normal level under the non-selected state when a signal is to be written into the memory cell.

Claim 18

A semiconductor memory according to claim 1, wherein said address voltage supply means comprises means for supplying an address voltage of the high level to said switched impedance elements, for the selected state, and further including means for increasing the voltage supplied to one of the digit lines of said pairs of digit lines, by an amount greater than difference between the voltages at the collectors of said transistors in the selected state but less than the difference between the voltage at the collectors of said transistors in the non-selected state.

Claim 19

a switched element supplied with the address voltage and presenting a high or a low impedance value in response to a low or a high level of the applied address voltage for providing or not providing a low value resistor in shunt with each high value resistor when the swItched element has a low or high impedance value, so that said collector bias source is connected to the collectors of said pair of transistors through said low value resistor when the address voltage has the high level or through at least said high value resistor when the address voltage has the low level, respectively.

Claim 20

a switched element supplied with the address voltage and presenting a high or a low impedance value in response to a low or a high level of the applied address voltage for providing or not providing a low value resistor in shunt with each high value resistor when the swItched element has a low or high impedance value, so that said collector bias source is connected to the collectors of said pair of transistors through said low value resistor when the address voltage has the high level or through at least said high value resistor when the address voltage has the low level, respectively.

Claim 21

a plurality of digit line pairs each including a pair of digit lines and correspondingly provided to the memory cells in each column in such a manner that the pairs of digit lines are commonly connected with the emitters of the respective pairs of transistors of the memory cells located in the same column of the matrix, respectively; b. means for applying selectively a row selecting address voltage to one of said address lines; c. means for applying selectively a column selecting address voltage to one of the digit line pairs; d. first holding means provided between the pair of digit lines in each digit line pair for preventing information stored in the respective memory cells from being destroyed when no row selecting address voltage and no column selecting address voltage are applied to the memory matrix; e. second holding means provided between the pair of digit lines in each digit line pair for preventing information stored in the memory cells located in the selected row and in the non-selected columns from being destroyed; f. first and second current sources, the former being connected commonly to one of the pairs Of digit lines of the respective digit line pairs and the latter being connected commonly to the other one of the pairs of digit lines of the respective digit line pairs, respectively, for flowing currents in the respective digit lines; g. a pair of information write-in means, one of which is connected commonly to one of the pairs of digit lines of the respective digit line pairs and the other of which is connected commonly to the other one of the respective digit line pairs, for applying a write-in voltage representing information to be stored in the associated digit lines; and h. information read-out means connected between the pairs of digit lines of the respective digit line pairs for reading-out information stored in the memory cell selected.

Claim 22

a plurality of digit line pairs each including a pair of digit lines and correspondingly provided to the memory cells in each column in such a manner that the pairs of digit lines are commonly connected with the emitters of the respective pairs of transistors of the memory cells located in the same column of the matrix, respectively; b. means for applying selectively a row selecting address voltage to one of said address lines; c. means for applying selectively a column selecting address voltage to one of the digit line pairs; d. first holding means provided between the pair of digit lines in each digit line pair for preventing information stored in the respective memory cells from being destroyed when no row selecting address voltage and no column selecting address voltage are applied to the memory matrix; e. second holding means provided between the pair of digit lines in each digit line pair for preventing information stored in the memory cells located in the selected row and in the non-selected columns from being destroyed; f. first and second current sources, the former being connected commonly to one of the pairs Of digit lines of the respective digit line pairs and the latter being connected commonly to the other one of the pairs of digit lines of the respective digit line pairs, respectively, for flowing currents in the respective digit lines; g. a pair of information write-in means, one of which is connected commonly to one of the pairs of digit lines of the respective digit line pairs and the other of which is connected commonly to the other one of the respective digit line pairs, for applying a write-in voltage representing information to be stored in the associated digit lines; and h. information read-out means connected between the pairs of digit lines of the respective digit line pairs for reading-out information stored in the memory cell selected.

Claim 23

a pair of switched impedance elements connected, respectively, in the collector circuits of said pair of transistors, each of said switched impedance elements presenting a high or a low impedance value when an address voltage supplied thereto has a high or a low level, respectively; b. a pair of digit lines coupled to said memory cell, said respective digit lines being connected to the respective emitters of said pair of transistors; c. a collector bias source coupled to said memory cell for supplying a collector bias voltage to the collectors of said pair of transistors through said switched impedance elements, respectively; and d. address voltage supply means connected to said switched impedance elements for supplying to said switched impedance elements an address voltage of the high or low level when said memory cell is selected or non-selected, respectively, and for causing both said switched impedance elements to present said high impedance value when the address voltage supplied thereto has said high level, so that both the collector impedances viewed from the respective collectors into said switched impedance elements are concurrently provided at the low or the high value when the memory cell is selected or non-selected, thereby attaining high speed operation in said memory cell.

Claim 24

a pair of switched impedance elements connected, respectively, in the collector circuits of said pair of transistors, each of said switched impedance elements presenting a high or a low impedance value when an address voltage supplied thereto has a high or a low level, respectively; b. a pair of digit lines coupled to said memory cell, said respective digit lines being connected to the respective emitters of said pair of transistors; c. a collector bias source coupled to said memory cell for supplying a collector bias voltage to the collectors of said pair of transistors through said switched impedance elements, respectively; and d. address voltage supply means connected to said switched impedance elements for supplying to said switched impedance elements an address voltage of the high or low level when said memory cell is selected or non-selected, respectively, and for causing both said switched impedance elements to present said high impedance value when the address voltage supplied thereto has said high level, so that both the collector impedances viewed from the respective collectors into said switched impedance elements are concurrently provided at the low or the high value when the memory cell is selected or non-selected, thereby attaining high speed operation in said memory cell.

Claim 25

In a semiconductor memory comprising: a. at least one memory cell which includes

Claim 26

In a semiconductor memory comprising: a. at least one memory cell which includes

Claim 27

An improvement in a semiconductor memory according to claim 4, which further comprises a coupling impedance element connected between the collectors of the pair of transistors for preventing said pair of transistors from saturating.

Claim 28

The improvement according to claim 5, wherein said coupling impedance element comprises a pair of Schottky barrier diodes connected in parallel with conductive directions opposite to each other.

Claim 29

The improvement according to claim 4, wherein each of said switched impedance elements comprises a high impedance element, a low impedance element and current control element which controls current flowing through the high impedance element to switch through the low impedance element in response to apply of the address voltage thereonto.

Claim 30

The improvement aCcording to claim 7, wherein there is provided a double-emitter transistor, the respective emitters of which are connected in series with the low impedance element of the respective switched impedance elements, so that the double-emitter transistor serve as the current control elements, the base of said double-emitter transistor being connected with the address line so as to be supplied with the address voltage, and the collector of said double-emitter transistor being supplied with a collector bias voltage.

Claim 31

The improvement according to claim 7, wherein each of said switched impedance elements is formed by a parallel circuit of said high impedance element and a series circuit of said low impedance element and said current control element, and said address voltage is incorporated in a collector bias voltage and applied to the respective current control elements in the respective collector circuits of said pair of transistors.

Claim 32

The improvement according to claim 9, wherein said current control elements are diodes.

Claim 33

The improvement according to claim 9, which further comprises a coupling resistor connected between the collectors of said pair of transistors.

Claim 34

The improvement according to claim 7, wherein there is provided a double-emitter transistor having two emitters, a base and a collector, the respective emitters of which are connected in series with the low impedance element and serve as the current control elements, the collector of which is supplied with a collector bias voltage and the base of which is supplied with the address voltage.

Claim 35

The improvement according to claim 12, wherein the collector bias voltage supplied to the collector of the double-emitter transistor is constant.

Claim 36

The improvement according to claim 12, wherein the collector bias voltage supplied to the collector of said double-emitter transistor incorporates therein the address voltage and is thus variable in response to change in level of the address voltage.

Claim 37

A semiconductor memory comprising: a. a memory matrix which includes

Claim 38

A semiconductor memory comprising: a. a memory matrix which includes

Claim 39

A semiconductor memory according to claim 15, wherein each pair of switched impedance elements comprises a double-emitter transistor having two emitters, a base and a collector, the respective emitters of which are connected in series with respective low impedance elements, each of which is connected to the collectors of each of said transistors of said pair of transistors, and the collector of said double-emitter transistor being connected to respective high impedance elements, which are also connected to the collectors of the transistors of said pair, the connection points between the collector of said double-emitter transistor and said high impedance elements being connected to a source of reference potential.

Claim 40

A semiconductor memory according to claim 16, wherein said address lines are connected to the bases of said double-emitter transistors within each of said memory cells.

Claim 41

A semiconductor memory according to claim 17, wherein said means for applying selectively a column selecting address voltage to one of said digit line pairs, comprises respective pairs of transistors, each transistor of said pair of transistors within said selectively applying means being connected to a respective one of said digit lines in said digit line pairs, and having said column selecting address voltage applied in common to the bases thereof.

Claim 42

A semiconductor memory according to claim 18, wherein said pair of information write-in means comprises a pair of input transistors, the emitters of which are connected commonly to the respective ones of the pairs of digit lines and to the bases of which are applied the write-in information.

Claim 43

A semiconductor memory according to claim 18, wherein said information read-out means comprises a sense-amplifier including a pair of multi-emitter transistors, the bases of which are connected in common to a source of reference potential and the respective multiple emitters of which are connected to respective common ones of said digit line pairs of said respective memory columns, the collectors of said pair of multi-emitter transistors of said sense amplifier providing the information to be read out from the memory cell which has been selectively addressed.

Claim 44

A semiconductor memory according to claim 20, including current sources respectively connected to the digit lines in respective columns through pairs of diodes connected between said current sources and each line in respective lines of digit lines in said columns.

Claim 45

A semiconductor memory according to claim 21, including a clamping transistor having a multi-emitter configuration, the respective emitters thereof being connected to the junctions of said respective diode pairs connected to said respective current sources, and to the base of which is connected a clamping voltage.

Claim 46

A semiconductor memory according to claim 22, wherein said means for applying selectively a column selecting address voltage to one of the digit line pairs further includes a reference level transistor having a multi-emitter configuration, the respective emitters of which are connected to respective pairs of digit lines in said respective columns, the reference voltage being applied to the base of said reference level transistor.

Claim 47

A semiconductor memory comprising: a. at least one memory cell including a pair of single emitter transistors and a pair of load impedance elements connected to the collectors of said pair of transistors, respectively, the collector of each said transistor being connected to the base of the other transistor, respectively; b. a source for flowing currents in said pair of transistors through the respective load impedance elements; c. a pair of digit lines connected to the emitters of said pair of transistors, respectively; d. an address line connected to said collector load impedance elements; e. an information write-in circuit connected to said digit lines for supplying a raised write-in voltage representing information to be stored to said pair of transistors; f. an information read-out circuit connected to said digit lines for deriving output signals from said memory cell; and g. an address circuit connected to said address line for applying an address voltage to said load impedance elements concurrently only when said address line is required to be selected, characterized in that said address circuit applies to said address line the address voltage of a high level when both the information write-in operation and the information read-out operation are required, and each of said pair collector load impedance elements is constituted by a switched impedance element which operatingly presents a low or a high impedance value in response to whether the address voltage is applied thereto or not, respectively, whereby high speed operation of said memory can be attained.

Claim 48

A semiconductor memory comprising: a. at least one memory cell including a pair of single emitter transistors and a pair of load impedance elements connected to the collectors of said pair of transistors, respectively, the collector of each said transistor being connected to the base of the other transistor, respectively; b. a source for flowing currents in said pair of transistors through the respective load impedance elements; c. a pair of digit lines connected to the emitters of said pair of transistors, respectively; d. an address line connected to said collector load impedance elements; e. an information write-in circuit connected to said digit lines for supplying a raised write-in voltage representing information to be stored to said pair of transistors; f. an information read-out circuit connected to said digit lines for deriving output signals from said memory cell; and g. an address circuit connected to said address line for applying an address voltage to said load impedance elements concurrently only when said address line is required to be selected, characterized in that said address circuit applies to said address line the address voltage of a high level when both the information write-in operation and the information read-out operation are required, and each of said pair collector load impedance elements is constituted by a switched impedance element which operatingly presents a low or a high impedance value in response to whether the address voltage is applied thereto or not, respectively, whereby high speed operation of said memory can be attained.

Claim 49

In a storage cell having two cross-coupled single emitter transistors each being provided with a high impedance load in its collector circuit and with a pair of digit lines at the emitter of the respective transistors, so as to form a bistable circuit with a storage state, a read cycle and a write cycle, the improvement which comprises: a pair of semiconductive switched impedance elements which are operatively rendered in a high or a low impedance state in response to an address voltage applied thereto of a low or a high level for providing a low impedance path in shunt with each impedance load when said switched impedance elements are in the low impedance state; and bilevel source means for supplying the address voltage of the high or the low level when the cell is to be selected or non-selected, respectively, and for rendering both said switched impedance elements in the high impedance state when said cell is in its non-selected state and at least one of said switched impedance elements in the low impedance state when said cell is in the selected state.

Claim 50

In a storage cell having two cross-coupled single emitter transistors each being provided with a high impedance load in its collector circuit and with a pair of digit lines at the emitter of the respective transistors, so as to form a bistable circuit with a storage state, a read cycle and a write cycle, the improvement which comprises: a pair of semiconductive switched impedance elements which are operatively rendered in a high or a low impedance state in response to an address voltage applied thereto of a low or a high level for providing a low impedance path in shunt with each impedance load when said switched impedance elements are in the low impedance state; and bilevel source means for supplying the address voltage of the high or the low level when the cell is to be selected or non-selected, respectively, and for rendering both said switched impedance elements in the high impedance state when said cell is in its non-selected state and at least one of said switched impedance elements in the low impedance state when said cell is in the selected state.

Claim 51

A semiconductor memory comprising: a. at least one memory cell including

Claim 52

A semiconductor memory comprising: a. at least one memory cell including

Claim 53

The semiconductor memory of claim 26, wherein both said switched impedance elements are rendered conductive when the address voltage supplied thereto is at a high level.

Claim 54

The semiconductor memory of claim 26, wherein said switched impedance elements are both forward biased diodes.

Claim 55

The semiconductor memory of claim 26, wherein said switched impedance elements are constituted of a multi-emitter transistor having two emitters each connected to the collector of each transistor, a base supplied thereto with the address voltage, and a collector connected to said source means.