Multiport memory array

Claim 2

A memory array having a plurality of memory storage elements, a first pair of access lines associated with said elements for providing precharged interrogate signals to said elements, and wherein each said element is arranged to respond to said precharged interrogate signals with the signal value stored thereat, said response occurring at a time immediately following the precharging of said first access lines, said elements further arranged to be isolated from said first access lines during said precharging interval, characterized in that there is provided a second pair of access lines associated with said elements, said second pair of access lines being independent from said first pair of access lines for providing precharged interrogate signals to said elements, said second pair of access lines being adapted to receive precharge interrogate signals at a time different from the precharging of interrogate signals on said first pair of access lines thereby allowing said associated elements to respond with the signal value stored thereat over said second pair of access lines independent from said response over said first pair of access lines.

Claim 3

The invention set forth in claim 1 wherein said precharging of said second pair of access lines is controlled from opposite clock phases of a precharge and read/write clock.

Claim 4

The invention set forth in claim 2 wherein said memory array is an NMOS array.

Claim 5

The invention set forth in claim 1 further comprising a first input/output register associated with said first pair of accessing lines and a second input/output register associated with said second pair of accessing lines, each said register arranged to generate said precharging interrogate signals in response to input signals applied thereto from an external source, said registers also arranged to provide said external source with said response signals from said associated memory elements.

Claim 6

A memory system operable for providing multiple single cycle access to a memory, said system comprising a memory array having a plurality of individually addressable memory storage elements, arranged in rows and columns, first clock control signals having a read/write signal, a precharge signal and column select signals, a first group of access lines, said group divided into pairs with individual pairs associated with said memory elements of each row for precharging interrogate signals to said row of elements under control of said precharge first clock signal, each said memory element arranged to respond to supplied interrogate signals and to said column select signals provided on a selected column with the signal value stored at each row of said selected column, said response controlled by said first clock read/write signal, said elements further arranged to be isolated from said first group of access lines during said precharging interval, second clock control signals having a read/write signal, a precharge signal and column select signals, said signals from said first and second clocks being oppositely phased, and a second group of access lines, said group divided into pairs with individual pairs associated with said memory elements, said second pair of access lines being independent from said first pair of access lines for precharging interrogate signals to said elements under control of said precharge second clock signals, each said memory element arranged to respond to supplied interrogate signals and said second clock column select signals provided on a second selected column with the signal value stored at each row of said second selected column, said response controlled by said second clock read/write signal.

Claim 7

A memory system operable for providing multiple single cycle access to a memory, said system comprising a memory array having a plurality of individually addressable memory storage elements, arranged in rows and columns, first clock control signals having a read/write signal, a precharge signal and column select signals, a first group of access lines, said group divided into pairs with individual pairs associated with said memory elements of each row for precharging interrogate signals to said row of elements under control of said precharge first clock signal, each said memory element arranged to respond to supplied interrogate signals and to said column select signals provided on a selected column with the signal value stored at each row of said selected column, said response controlled by said first clock read/write signal, said elements further arranged to be isolated from said first group of access lines during said precharging interval, second clock control signals having a read/write signal, a precharge signal and column select signals, said signals from said first and second clocks being oppositely phased, and a second group of access lines, said group divided into pairs with individual pairs associated with said memory elements, said second pair of access lines being independent from said first pair of access lines for precharging interrogate signals to said elements under control of said precharge second clock signals, each said memory element arranged to respond to supplied interrogate signals and said second clock column select signals provided on a second selected column with the signal value stored at each row of said second selected column, said response controlled by said second clock read/write signal.

Claim 8

The invention set forth in claim 5 wherein said memory array is an NMOS array.

Claim 9

A memory array having a plurality of individually addressable memory storage elements said elements arranged in columns and rows, means for addressing each column of said memory storage elements, said means including first and second access registers, and first and second selectors associated with said element columns, a first pair of access lines associated with each row of said elements and with said first access register for providing first and second precharged activation signals to a particular one of said elements within said row identified jointly by signals from said first access register and said first selector, a second pair of access lines associated with each row of said elements and with said second access register for providing first and second precharged activation signals to a particular one of said elements within said row identified jointly by signals from said second access register and said second selector, each said element arranged to respond to said first precharged activation signals with the signal value stored thereat, and to respond to said second precharged activation signal by storing at said element a signal value provided at the corresponding access register, each said response occurring at a time immediately following the precharging of said access lines, said elements further arranged to be isolated from said access lines during said corresponding precharging interval.

Claim 10

A memory array having a plurality of individually addressable memory storage elements said elements arranged in columns and rows, means for addressing each column of said memory storage elements, said means including first and second access registers, and first and second selectors associated with said element columns, a first pair of access lines associated with each row of said elements and with said first access register for providing first and second precharged activation signals to a particular one of said elements within said row identified jointly by signals from said first access register and said first selector, a second pair of access lines associated with each row of said elements and with said second access register for providing first and second precharged activation signals to a particular one of said elements within said row identified jointly by signals from said second access register and said second selector, each said element arranged to respond to said first precharged activation signals with the signal value stored thereat, and to respond to said second precharged activation signal by storing at said element a signal value provided at the corresponding access register, each said response occurring at a time immediately following the precharging of said access lines, said elements further arranged to be isolated from said access lines during said corresponding precharging interval.