US3916394A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed random access memory
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-12-09
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Granted: 1975-10-28
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Expires: 1994-12-09
Abstract
Abstract A bipolar RAM has increased speed through use of nonsaturating voltages and improved read/write capabilities provided by memory cell and isolation circuit which functions as a sense amplifier. An output buffer including constant current means provides an output responsive to the signal from the memory cells taken through the isolation circuitry.
Inventors
- 👤 Darrell L Fett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; Y; Y10; Y10S; Y10S148/00; Y10S148/169
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
280 words
A random access memory comprising: A. a plurality of memory cells arranged in rows and columns and selectively addressable for read or write operations, each cell comprising a pair of plural emitter bipolar transistors with conductive means connecting the base of each transisTor to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, first addressing means connected to a first emitter of each of said pair of transistors, a first output connected to a second emitter of one transistor, and a second output connected to a second emitter of the other transistor; B. address decoding means for selectively addressing said plurality of memory cells; C. output circuit means including a plurality of isolation circuits each connected to one output of each cell in each column of memory cells, said isolation circuit comprising first and second bipolar transistors with conductive means interconnecting the emitters of said first and second transistors, resistive means connecting said conductive means to a first voltage potential, means connecting said conductive means to said memory cell outputs, a write control line connected to the base of said first transistor, a reference voltage potential connected to the base of said second transistor, means connecting the collectors of said first and second transistors to a second voltage potential, and a third bipolar transistor, means connecting the collector of said second transistor to the base of said third transistor, means connecting the collector of said third transistor to said second voltage potential, and memory output means connected to the emitter of said third transistor; and D. read/write control means for controlling said output circuit means for respective read and write operations.
Claim 2
Dependent Claim
280 words
A random access memory comprising: A. a plurality of memory cells arranged in rows and columns and selectively addressable for read or write operations, each cell comprising a pair of plural emitter bipolar transistors with conductive means connecting the base of each transisTor to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, first addressing means connected to a first emitter of each of said pair of transistors, a first output connected to a second emitter of one transistor, and a second output connected to a second emitter of the other transistor; B. address decoding means for selectively addressing said plurality of memory cells; C. output circuit means including a plurality of isolation circuits each connected to one output of each cell in each column of memory cells, said isolation circuit comprising first and second bipolar transistors with conductive means interconnecting the emitters of said first and second transistors, resistive means connecting said conductive means to a first voltage potential, means connecting said conductive means to said memory cell outputs, a write control line connected to the base of said first transistor, a reference voltage potential connected to the base of said second transistor, means connecting the collectors of said first and second transistors to a second voltage potential, and a third bipolar transistor, means connecting the collector of said second transistor to the base of said third transistor, means connecting the collector of said third transistor to said second voltage potential, and memory output means connected to the emitter of said third transistor; and D. read/write control means for controlling said output circuit means for respective read and write operations.
Claim 3
Dependent Claim
27 words
A random access memory as defined by claim 1 wherein each memory cell includes second addressing means connected to third emitters of said first and second transistors.
Claim 4
Dependent Claim
35 words
A random access memory as defined by claim 2 wherein said output memory means further includes an output buffer circuit with means for selectively enabling said buffer circuit in response to said read/write control means.
Claim 5
Dependent Claim
89 words
A random access memory as defined by claim 3 wherein said output buffer circuit includes a constant current source, a first transistor switch operable in response to a stored 1 as transmitted through an isolation circuit to provide a real data output from said constant current source, a second transistor switch operable in response to a stored 0 as transmitted through an isolation circuit to provide a complement data output from said constant current source, and enabling means for enabling data readout in response to a read control signal.
Claim 6
Dependent Claim
52 words
A random access memory as defined by claim 3 wherein said read/write control means comprises gate means interconnected and responsive to an enable signal, a data-in signal, and a read or write signal to effect the reading of a memory cell or the writing of a data bit into a memory cell.
Claim 7
Dependent Claim
148 words
A random access memory as defined by claim 5 wherein said addressing decoding means comprises a first plurality of transistors having emitter and collector terminals connected in parallel, a first transistor with emitter connected to the emitters of said first plurality of transistors and collector connected to a first voltage potential, resistive means connecting said first voltage potential to said collectors of said first plurality of transistors, resistive means connecting the emitters of said first plurality of transistors and said first transistor to a second voltage potential, a second bipolar transistor, conductive means connecting the collector of said second transistor to said first voltage potential, resistive means connecting the emitter of said second transistor to said second voltage potential, conductive means connecting the base of said second transistor to the collectors of said first plurality of transistors, and output means connected to the collector of said second transistor.
Claim 8
Dependent Claim
256 words
For use in a random access memory, a memory cell comprising a plurality of memory cells arranged in rows and columns and selectively addressable for read or write operations, each cell comprising a pair of plural emitter bipolar transistors with conductive means connecting the base of each transistor to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, first addressing means connected to a first emitter of each of said pair of transistors, a first output connected to a second emitter of one transistor, and a second output connected to a second emitter of the other transistor, and output circuit means including a plurality of isolation circuits each connected to one output of each cell in each column of memory cells, said isolation circuit comprising first and second bipolar transistors with conductive means interconnecting the emitters of said first and second transistors, resistive means connecting said conductive means to a first voltage potential, means connecting said conductive means to said memory cell outputs, a write control line connected to the base of said first transistor, a reference voltage potential connected to the base of said second transistor, means connecting the collectors of said first and second transistors to a second voltage potential, and a third bipolar transistor, means connecting the collector of said second transistor to the base of said third transistor, means connecting the collector of said third transistor to said second voltage potential, and memory output means connected to the emitter of said third transistor.
Claim 9
Dependent Claim
256 words
For use in a random access memory, a memory cell comprising a plurality of memory cells arranged in rows and columns and selectively addressable for read or write operations, each cell comprising a pair of plural emitter bipolar transistors with conductive means connecting the base of each transistor to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, first addressing means connected to a first emitter of each of said pair of transistors, a first output connected to a second emitter of one transistor, and a second output connected to a second emitter of the other transistor, and output circuit means including a plurality of isolation circuits each connected to one output of each cell in each column of memory cells, said isolation circuit comprising first and second bipolar transistors with conductive means interconnecting the emitters of said first and second transistors, resistive means connecting said conductive means to a first voltage potential, means connecting said conductive means to said memory cell outputs, a write control line connected to the base of said first transistor, a reference voltage potential connected to the base of said second transistor, means connecting the collectors of said first and second transistors to a second voltage potential, and a third bipolar transistor, means connecting the collector of said second transistor to the base of said third transistor, means connecting the collector of said third transistor to said second voltage potential, and memory output means connected to the emitter of said third transistor.
References Cited (Backward Citations)
US3821719A
Cited
US3764825A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |