Semiconductor circuit

Claim 2

A semiconductor circuit comprising a first node, a second node, first means for supplying said first node with a logic signal, a first field effect transistor coupled between said first and second nodes, means for operatively making said first transistor conducting thereby to provide said second node with a signal at said first node, a power supply terminal, a second field effect transistor, means for connecting one of a source and a drain of said second transistor to said power supply terminal, means for connecting the other of the source and drain of said second transistor to said second node, a delay circuit having an input terminal coupled to said second node, a true output terminal and a complement output terminal, a third field effect transistor, means for connecting one of a source and a drain of said third transistor to said second node, means for connecting a gate of said third transistor to said complement output terminal, means for connecting the other of the source and drain of said third transistor to a gate of said second transistor, a capacitor, means for connecting one end of said capacitor to the gate of said second transistor and means for connecting the other end of said capacitor to said true output terminal.

Claim 3

The circuit according to claim 1, in which said first means includes a flip-flop circuit.

Claim 4

The circuit according to claim 1, in which said delay circuit includes a first series circuit of fourth and fifth field effect transistors, a second series circuit of sixth and seventh field effect transistors, a third series circuit of eighth and ninth field effect transistors, means for connecting a gate of said fourth transistor to said input terminal, means for supplying gates of said fifth and sixth transistors with a reset signal for initializing a state of said delay circuit, means for connecting an intermediate junction of said first series circuit to a gate of said seventh field effect transistor, means for connecting an intermediate junction of said second series circuit to a gate of said ninth transistor, means for connecting the intermediate junction of said second series circuit to said complement output terminal, and means for connecting an intermediate junction of said third series circuit to said true output terminal.

Claim 5

A semiconductor circuit comprising a first node, a second node, switching means coupled between said first node and said second node, means for operatively enabling said switching means thereby to make a level at said second node substantially equal to that at said first node, a potential terminal receiving a given potential, a first field effect transistor, means for connecting one of a source and a drain of said first transistor to said second node, means for connecting the other of the source and drain of said first transistor to said potential terminal, a third node, means for connecting a gate of said first transistor to said third node, and means for operatively raising a potential at said third node to a level having a higher absolute value than said given potential by a bootstrap effect after a level at said second node becomes a level nearly equal to said given potential.

Claim 6

A semiconductor circuit comprising a first node, a second node, switching means coupled between said first node and said second node, means for operatively enabling said switching means thereby to make a level at said second node substantially equal to that at said first node, a potential terminal receiving a given potential, a first field effect transistor, means for connecting one of a source and a drain of said first transistor to said second node, means for connecting the other of the source and drain of said first transistor to said potential terminal, a third node, means for connecting a gate of said first transistor to said third node, and means for operatively raising a potential at said third node to a level having a higher absolute value than said given potential by a bootstrap effect after a level at said second node becomes a level nearly equal to said given potential.

Claim 7

The circuit according to claim 4, in which said raising means includes a second field effect transistor, means for connecting one of a drain and a source of said second transistor to said second node, means for connecting the other of the drain and source of said second transistor to a gate of said first transistor, a capacitor, means for connecting one end of said capacitor to the gate of said first transistor, a delay circuit having an input terminal coupled to said second node, a true output terminal and a complement output terminal, means for connecting a gate of said second transistor to said complement output terminal, and means for connecting the other end of said capacitor to said true output terminal.

Claim 8

The circuit according to claim 4, in which said switching means includes a third field effect transistor coupled between said first and second nodes.

Claim 9

The circuit according to claim 4, further comprising means for operatively setting a potential at said second node at a reference potential prior to conducting of said switching means.

Claim 10

A semiconductor circuit comprising a first node to which a logic signal is applied, a first terminal to which a first potential is applied to, a second terminal to which a second potential is applied, a first series circuit of first and second field effect transistors connected in series between said first and second terminals and receiving a signal from said first node, a second series circuit of third and fourth field effect transistors connected in series between said first and second terminals and receiving a signal derived from an intermediate junction of said first series circuit, a third series circuit of fifth and sixth field effect transistors connected in series between said first and second terminals and receiving a signal derived from an intermediate junction of said second series circuit, a seventh field effect transistor coupled between said first terminal and said first node, a capacitor coupled between a gate of said fifth transistor and an intermediate junction of said third series circuit, means for connecting the gate of said fifth transistor to a gate of said seventh transistor, an eighth field effect transistor, first means for connecting one of a source and a drain of said eighth transistor to said first node, second means for connecting the other of the source and drain of said eighth field effect transistor to the gate of said fifth transistor, and third means for connecting a gate of said eighth transistor to the intermediate junction of said second series circuit.

Claim 11

A semiconductor circuit comprising a first node to which a logic signal is applied, a first terminal to which a first potential is applied to, a second terminal to which a second potential is applied, a first series circuit of first and second field effect transistors connected in series between said first and second terminals and receiving a signal from said first node, a second series circuit of third and fourth field effect transistors connected in series between said first and second terminals and receiving a signal derived from an intermediate junction of said first series circuit, a third series circuit of fifth and sixth field effect transistors connected in series between said first and second terminals and receiving a signal derived from an intermediate junction of said second series circuit, a seventh field effect transistor coupled between said first terminal and said first node, a capacitor coupled between a gate of said fifth transistor and an intermediate junction of said third series circuit, means for connecting the gate of said fifth transistor to a gate of said seventh transistor, an eighth field effect transistor, first means for connecting one of a source and a drain of said eighth transistor to said first node, second means for connecting the other of the source and drain of said eighth field effect transistor to the gate of said fifth transistor, and third means for connecting a gate of said eighth transistor to the intermediate junction of said second series circuit.

Claim 12

The circuit according to claim 8, in which said third means includes a ninth field effect transistor coupled between the gate of said eighth transistor and the intermediate junction and having a gate coupled to said first terminal.