US4267465A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for recharging the output nodes of field effect transistor circuits
Assignee: International Business Machines Corp
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Filing: 1979-01-15
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Granted: 1981-05-12
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Expires: 1999-01-15
Abstract
Abstract A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.
Inventors
- 👤 Werner Haug
- 👤 Joerg Gschwendtner
- 👤 Robert Schnadt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A circuit for recharging the input capacity of a circuit connected to the output of an FET driver circuit comprising: a first FET having a source electrode for supplying current to recharge the input capacitance connected to the output node of the driver circuit, a drain electrode connected to an operating voltage source, and a gate electrode connected to one electrode of a capacitor whose other electrode is connected to a periodic pulse source, a second FET having its source connected to said source of the first FET, a drain electrode connected to the gate of the first FET, and a gate electrode connected to the operating voltage source, said second FET sensing the potential at the source electrode of the first FET and transferring said potential to the gate of said first FET when the output node of the driver circuit is at a low potential with respect to the operating voltage to prevent current flowing through the first FET.
Claim 2
Dependent Claim
161 words
A circuit for recharging the input capacity of a circuit connected to the output of an FET driver circuit comprising: a first FET having a source electrode for supplying current to recharge the input capacitance connected to the output node of the driver circuit, a drain electrode connected to an operating voltage source, and a gate electrode connected to one electrode of a capacitor whose other electrode is connected to a periodic pulse source, a second FET having its source connected to said source of the first FET, a drain electrode connected to the gate of the first FET, and a gate electrode connected to the operating voltage source, said second FET sensing the potential at the source electrode of the first FET and transferring said potential to the gate of said first FET when the output node of the driver circuit is at a low potential with respect to the operating voltage to prevent current flowing through the first FET.
Claim 3
Dependent Claim
58 words
A circuit as in claim 1 including: a third FET between the periodic pulse source and capacitor having a drain electrode connected to the periodic pulse source, a gate electrode connected to its source electrode through a second capacitor, and connected to the output node through a fourth FET whose gate is connected to the operating voltage source.
Claim 4
Dependent Claim
158 words
A flip-flop circuit having two branches, each branch of said circuit comprising: a first FET having a source electrode for supplying current to recharge the input capacitance connected to the output node of the branch of the flip-flop circuit, a drain electrode connected to an operating voltage source, a gate electrode connected to one electrode of a capacitor whose other electrode is connected to a periodic pulse source, a second FET having its source connected to the source of the first FET, a drain electrode connected to the gate of the first FET, and a gate electrode connected to the operating voltage source, said second FET sensing the potential at the source electrode of the first FET and transferring said potential to the gate of said first FET when the output mode of the branch of the flip-flop circuit is at a low potential with respect to the operating voltage to prevent current flowing through the first FET.
Claim 5
Dependent Claim
158 words
A flip-flop circuit having two branches, each branch of said circuit comprising: a first FET having a source electrode for supplying current to recharge the input capacitance connected to the output node of the branch of the flip-flop circuit, a drain electrode connected to an operating voltage source, a gate electrode connected to one electrode of a capacitor whose other electrode is connected to a periodic pulse source, a second FET having its source connected to the source of the first FET, a drain electrode connected to the gate of the first FET, and a gate electrode connected to the operating voltage source, said second FET sensing the potential at the source electrode of the first FET and transferring said potential to the gate of said first FET when the output mode of the branch of the flip-flop circuit is at a low potential with respect to the operating voltage to prevent current flowing through the first FET.
Claim 6
Dependent Claim
63 words
A flip-flop circuit as in claim 3 wherein each branch further comprises: A third FET between the periodic pulse source and capacitor having a drain electrode connected to the periodic pulse source, a gate electrode connected to its source electrode through a second capacitor, and connected to the output node through a fourth FET whose gate is connected to the operating voltage source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-11 | 1984-11-10 | 1985-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-11 | 1988-11-10 | 1989-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-11 | 1992-11-10 | 1993-05-12 | $7700.00 | Window Closed / Lapsed |