Patent US4385947A successfully refreshed from Google Patents.
US4385947A
Expired / Lapsed
US
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Method for fabricating CMOS in P substrate with single guard ring using local oxidation
Assignee: Harris Corp
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Filing: 1981-07-29
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Granted: 1983-05-31
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Expires: 2001-07-29
Abstract
Abstract CMOS transistors are fabricated in a P substrate by applying a first mask with an opening for introducing N type impurities to form a well, applying a second mask layer of oxidation inhibiting material over the region in which the transistors are to be formed; applying a third mask layer over the well, introducing P type impurities into the surface of the substrate using the second and third masking layers to form a guard ring except in the N- well regions and the regions in which the N channel MOS transistors are to be formed, oxidizing the substrate using said second mask to form a thick oxide layer on said substrate except on the transistor regions with the guard ring vertically displaced from the regions in which the transistors are to be formed, introducing P impurities in the channel region of the CMOS transistors and forming CMOS transistors in said transistor regions. A CMOS process capable of the fabrication of N and P channel devices with channel lengths down to the submicron region by the proper adjustment of doping levels and implant doses in the N type well and the P and N channel regions, with no major changes in the basic process flow.
Inventors
- 👤 Mark A. Halfacre
- 👤 David S. Pan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:41
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
228 words
A method of fabricating complementary insulated gate field effect transistors in a P conductivity type substrate having a P conductivity type impurity concentration of 1×10 14 to 5×10 15 carriers per cubic centimeter comprising: forming a first masking layer over said substrate with a first opening to define the surface area of a P channel device; introducing N impurities into said substrate through said first opening to form an N conductivity type well region in said substrate having a surface N conductivity type impurity concentration of 1×10 15 to 3×10 16 carriers per cubic centimeter; removing said first masking layer; forming an oxide inhibiting second masking layer over regions in which the source, drain and channel of the transistors are to be formed; forming a third masking layer on said second masking layer and said substrate over only said well region; introducing P impurities into said substrate to form a P conductivity type guard ring of a greater impurity concentration than said substrate in said substrate except at said well region and the N channel transistor region of said substrate; removing said third masking layer; oxidizing said substrate to form a thick oxide layer on said substrate except on said transistor regions as defined by said second masking layer; removing said second masking layer to expose said transistor regions; and forming said transistors in said exposed transistor regions.
Claim 2
Independent Claim
228 words
A method of fabricating complementary insulated gate field effect transistors in a P conductivity type substrate having a P conductivity type impurity concentration of 1×10 14 to 5×10 15 carriers per cubic centimeter comprising: forming a first masking layer over said substrate with a first opening to define the surface area of a P channel device; introducing N impurities into said substrate through said first opening to form an N conductivity type well region in said substrate having a surface N conductivity type impurity concentration of 1×10 15 to 3×10 16 carriers per cubic centimeter; removing said first masking layer; forming an oxide inhibiting second masking layer over regions in which the source, drain and channel of the transistors are to be formed; forming a third masking layer on said second masking layer and said substrate over only said well region; introducing P impurities into said substrate to form a P conductivity type guard ring of a greater impurity concentration than said substrate in said substrate except at said well region and the N channel transistor region of said substrate; removing said third masking layer; oxidizing said substrate to form a thick oxide layer on said substrate except on said transistor regions as defined by said second masking layer; removing said second masking layer to expose said transistor regions; and forming said transistors in said exposed transistor regions.
Claim 3
Dependent Claim
38 words
The method according to claim 1 wherein said oxidizing forms said thick oxide layer penetrating into said substrate less than the depth of said well region and displaces said guard ring from the surface of said transistor regions.
Claim 4
Dependent Claim
42 words
The method according to claim 2 wherein forming said transistors includes introducing impurities into said transistor regions to form source and drain regions, said source and drain regions having a depth less than the depth of penetration of said thick oxide layer.
Claim 5
Dependent Claim
61 words
The method according to claim 3 wherein forming said transistors includes forming a thin insulative layer over said transistor regions, forming a layer of gate material over said insulative layer, removing portions of said insulative layer and said gate layer to define a gate structure, and said impurities are introduced into said openings using said gate structure as an alignment mask.
Claim 6
Dependent Claim
26 words
The method according to claim 1 including initially forming a thin oxide layer on the substrate and forming said first opening in said thin oxide layer.
Claim 7
Dependent Claim
45 words
The method according to claim 5 wherein said thin oxide layer is sufficiently thick to form a mask with said second masking layer to prevent introduction of said P conductivity type impurities into said N channel transistor region not covered by said third masking layer.
Claim 8
Dependent Claim
38 words
The method according to claim 5 wherein said first opening in said thin oxide layer is formed by applying, exposing and etching a layer of photosensitive resist material and said photosensitive resist material forming said first masking layer.
Claim 9
Dependent Claim
25 words
The method according to claim 5 wherein said thin oxide layer is formed to have a thickness in the range of 500 to 1000 angstroms.
Claim 10
Dependent Claim
22 words
The method according to claim 5 including removing any oxide over said transistor regions before forming said transistors in said transistor regions.
Claim 11
Dependent Claim
14 words
The method according to claim 9 wherein said oxide is removed by non-selective etching.
Claim 12
Dependent Claim
17 words
The method according to claim 1 wherein said first and third masking layers are photosensitive resist materials.
Claim 13
Dependent Claim
27 words
The method according to claim 1 including introducing P conductivity type impurities into the surface of said transistor regions before forming said transistors in said transistor regions.
Claim 14
Independent Claim
148 words
A method of fabricating complementary insulated gate field effect transistors having a channel length in the micron range comprising: introducing N type impurities into a P substrate to form an N conductivity type well region in said P substrate having an impurity concentration sufficient to prevent punchthrough for a desired P channel transistor; introducing P type impurities into a P type region of said substrate to increase the impurity concentration of the surface of said P type region to determine the threshold voltage and prevent punchthrough for a desired N channel transistor; introducing P type impurities into said N type well region to reduce the N type impurity concentration of the surface of said N type to determine the threshold voltage of said desired P channel device; and forming an N channel transistor in said P type region and a P channel transistor in said N type well.
Claim 15
Independent Claim
148 words
A method of fabricating complementary insulated gate field effect transistors having a channel length in the micron range comprising: introducing N type impurities into a P substrate to form an N conductivity type well region in said P substrate having an impurity concentration sufficient to prevent punchthrough for a desired P channel transistor; introducing P type impurities into a P type region of said substrate to increase the impurity concentration of the surface of said P type region to determine the threshold voltage and prevent punchthrough for a desired N channel transistor; introducing P type impurities into said N type well region to reduce the N type impurity concentration of the surface of said N type to determine the threshold voltage of said desired P channel device; and forming an N channel transistor in said P type region and a P channel transistor in said N type well.
Claim 16
Dependent Claim
16 words
The method according to claim 13 wherein said P type impurities introduction steps are performed simultaneously.
Claim 17
Dependent Claim
62 words
The method according to claim 13 wherein said substrate is selected to have a P conductivity type impurity concentration in the range of 1×10 14 to 5×10 15 carriers per cubic centimeter and said first mentioned P type impurity introduction step is performed to increase the surface impurity concentration in the range of 5×10 15 to 1×10 17 carriers per cubic centimeter.
Claim 18
Dependent Claim
68 words
The method according to claim 13 wherein said N type impurity introduction step is performed to form said N type well having an impurity concentration in the range of 1×10 15 to 3×10 16 carriers per cubic centimeter and said second mentioned P type impurity introduction step is performed to reduce the surface impurity concentration in the range of -7×10 16 to 2.5×10 16 carriers per cubic centimeter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-30 | 1986-11-29 | 1987-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-30 | 1990-11-29 | 1991-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-30 | 1994-11-29 | 1995-05-31 | $7700.00 | Window Closed / Lapsed |