Capacitor memory and methods for reading, writing, and fabricating capacitor memories

Claim 2

A capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell being described by a voltage versus capacitance relationship which shifts along a voltage axis under the effect of applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying the second dielectric insulating layer, the second dielectric insulating layer overlying the doped substrate, and the doped substrate overlying the second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, said substrate having a doping concentration in a region near said second dielectric insulating layer of between 4×10 15 and 1×10 17 impurity atoms per cubic centimeter, said doping concentration having a distribution which is uniform in said substrate, and means for selectively applying an avalanching potential difference between first and second high conductivity layers for producing avalanche breakdown across selected cell substrate portions adjacent said second dielectric layer.

Claim 3

A capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell being described by a voltage versus capacitance relationship which shifts along a voltage axis under the effect of applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying the second dielectric insulating layer, the second dielectric insulating layer overlying the doped substrate, and the doped substrate overlying the second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, said substrate having a doping concentration in a region near said second dielectric insulating layer of between 4×10 15 and 1×10 17 impurity atoms per cubic centimeter, said doped substrate having a uniform conductivity type, and the cells associated with one second path being isolated from cells associated with the other remaining second paths by a substrate contacting amorphous silicon layer, and means for selectively applying an avalanching potential difference between first and second high conductivity layers for producing avalanche breakdown across selected cell substrate portions adjacent said second dielectric layer.

Claim 4

A capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell being described by a voltage versus capacitance relationship which shifts along a voltage axis under the effect of applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying the second dielectric insulating layer, the second dielectric insulating layer overlying the doped substrate, and the doped substrate overlying the second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, said substrate having a doping concentration in a region near said second dielectric insulating layer of between 4×10 15 and 1×10 17 impurity atoms per cubic centimeter, said doped substrate having a uniform conductivity type, and the cells associated with one second path being isolated from cells associated with the other remaining second paths by a substrate contacting amorphous silicon layer, and means for selectively applying an avalanching potential difference between first and second high conductivity layers for producing avalanche breakdown across selected cell substrate portions adjacent said second dielectric layer.

Claim 5

A capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell being described by a voltage versus capacitance relationship which shifts along a voltage axis under the effect of applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying the second dielectric insulating layer, the second dielectric insulating layer overlying the doped substrate, and the doped substrate overlying the second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, said substrate having a doping concentration in a region near said second dielectric insulating layer of between 4×10 15 and 1×10 17 impurity atoms per cubic centimeter, said doped substrate having a uniform conductivity type and the cells associated with one second path being isolated from cells associated with the other remaining second paths by a substrate contacting silicon dioxide barrier, and means for selectively applying an avalanching potential difference between first and second high conductivity layers for producing avalanche breakdown aross selected cell substrate portions adjacent said second dielectric layer.

Claim 6

A capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell being described by a voltage versus capacitance relationship which shifts along a voltage axis under the effect of applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying the second dielectric insulating layer, the second dielectric insulating layer overlying the doped substrate, and the doped substrate overlying the second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, said substrate having a doping concentration in a region near said second dielectric insulating layer of between 4×10 15 and 1×10 17 impurity atoms per cubic centimeter, said doped substrate having a uniform conductivity type and the cells associated with one second path being isolated from cells associated with the other remaining second paths by a substrate contacting silicon dioxide barrier, and means for selectively applying an avalanching potential difference between first and second high conductivity layers for producing avalanche breakdown aross selected cell substrate portions adjacent said second dielectric layer.

Claim 7

In a capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell exhibiting a measurable hysteresis characteristic under applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying said second dielectric insulating layer, the second dielectric layer overlying said doped substrate, and the doped substrate overlying said second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, and one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, the improvement comprising said substrate being uniformly doped to provide avalanche breakdown across a depletion region of said substrate at a potential between 6 and 50 volts, and means for selectively applying an avalanching potential difference across said first and second conductivity layers for producing said avalanche breakdown across the depletion region of selected cells adjacent said second dielectric layer.

Claim 8

In a capacitor memory array comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell exhibiting a measurable hysteresis characteristic under applied potentials, each capacitor cell comprising a plurality of material layers, the layers including at least a first high conductivity layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor substrate, and a second high conductivity layer, and said layers being arranged with said first conductivity layer overlying said first dielectric insulating layer, the first dielectric insulating layer overlying said second dielectric insulating layer, the second dielectric layer overlying said doped substrate, and the doped substrate overlying said second conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said first conductivity layers to form isolated first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form isolated second conductivity paths, and one each of said first and second conductivity paths uniquely identifying at a crossover position one capacitor cell of said memory array, the improvement comprising said substrate being uniformly doped to provide avalanche breakdown across a depletion region of said substrate at a potential between 6 and 50 volts, and means for selectively applying an avalanching potential difference across said first and second conductivity layers for producing said avalanche breakdown across the depletion region of selected cells adjacent said second dielectric layer.

Claim 9

The capacitor memory array of claim 4 wherein said substrate has a thickness comparable to a maximum depletion layer thickness for said capacitor memory cells.

Claim 10

In a metal-nitride-oxide-silicon capacitor memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each cell comprising a plurality of material layers arranged in sequence, said layers including a conductive metal layer, an insulating silicon nitride layer, an insulating silicon dioxide layer, a doped silicon substrate layer, and a high conductivity layer, the metal layer overlying the nitride layer, the nitride layer overlying the dioxide layer, the dioxide layer overlying the substrate layer and the substrate in contact with the conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said metal layers to form first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form second conductivity paths, each pair of first and second conductivity paths uniquely identifying at a crossover position one cell, and said oxide layer having a thickness less than about 50 Angstroms, the improvement comprising said substrate being uniformly doped to provide a low voltage avalanche breakdown across a depletion layer at a potential less than about 50 and greater than about 6 volts, and means for selectively applying an avalanching potential difference across said conductive metal layer and said high conductivity layer for producing said avalanche breakdown across the depletion region of selected cells adjacent said dioxide layer.

Claim 11

In a metal-nitride-oxide-silicon capacitor memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each cell comprising a plurality of material layers arranged in sequence, said layers including a conductive metal layer, an insulating silicon nitride layer, an insulating silicon dioxide layer, a doped silicon substrate layer, and a high conductivity layer, the metal layer overlying the nitride layer, the nitride layer overlying the dioxide layer, the dioxide layer overlying the substrate layer and the substrate in contact with the conductivity layer, a first plurality of interconnection paths, each path interconnecting a group of said metal layers to form first conductivity paths, a second plurality of interconnection paths, each second path interconnecting a group of said second high conductivity layers to form second conductivity paths, each pair of first and second conductivity paths uniquely identifying at a crossover position one cell, and said oxide layer having a thickness less than about 50 Angstroms, the improvement comprising said substrate being uniformly doped to provide a low voltage avalanche breakdown across a depletion layer at a potential less than about 50 and greater than about 6 volts, and means for selectively applying an avalanching potential difference across said conductive metal layer and said high conductivity layer for producing said avalanche breakdown across the depletion region of selected cells adjacent said dioxide layer.

Claim 12

The metal-nitride-oxide-silicon capacitor memory of claim 6 in which said substrate has a thickness comparable to a maximum depletion layer thickness for said capacitor memory cells.