Abstract An electronic memory apparatus is disclosed in which the memory element is an insulated gate field effect transistor (IGFET) whose gate contains a metal electrode located on top of two parallel layered insulators, such as silicon oxide and zinc sulfide. The memory of a signal voltage applied to the gate electrode is provided by the phenomenon of tunneling of electrical charges between the metal electrode and the interface between the two insulator layers. These charges are trapped at this interface until a voltage of opposite sign is applied which is sufficient to discharge (''''erase'''' ) the trapped charges at the interface. Nondestructive readout of the presence or absence of these trapped charges is afforded by monitoring the sourcedrain current in the transistor.
The memory apparatus recited in claim 1 in which the semiconductor includes first and second regions having a conductivity type opposite from at least the portion of the semiconductor upon which the insultator1 layer is in physical contact, and a first and a second electrode in physical contact with the first and the second regions, respectively, thereby forming a field effect transistor in which the first and second electrodes from the source and drain electrodes and the metal layer forms the gate electrode.
Claim 2
Dependent Claim
16 words
The memory element of claim 1 in which the second layer is approximately 1,000 A. thick.
Claim 3
Dependent Claim
25 words
The memory element of claim 1 in which the second layer is approximately 1,000 A. thick and the first layer is about 500 A. thick.
Claim 4
Dependent Claim
28 words
The memory element of claim 1 in which the first layer is of a material taken from the group consisting of silicon oxide, zirconium oxide, and aluminum oxide.