Integrated CMOS process with JFET

Claim 1

In a CMOS integrated circuit wafer treatment process, the additional steps for creating a JFET comprising: starting with a semiconductor wafer of a first conductivity type; establishing an opposite conductivity type well in said wafer with said well having a resistivity suitable for a JFET gate; creating spaced apart source and drain regions of said first conductivity type in said well; creating a channel region having said first conductivity type joining said source and drain regions; ion implanting an impurity of said opposite conductivity type having a different diffusity rate from the impurity in said channel to form an overlapping top cap over said channel to locate said channel below the surface of said wafer and whereby said top cap is connected to said well; applying operating potentials to said JFET; measuring the pinch off voltage of said JFET channel; and heat treating said wafer to shift said pinch off voltage.