Divide by three clock divider with symmetrical output

Claim 2

A divide by three digital clock divider circuit providing a symmetrical output, comprising: flip-flop means for receiving clock pulses of frequency F; and second means for alternately setting and resetting said flip-flop means on alternate inverted third clock pulse edges, and for maintaining the set and reset states of said flip-flop means for two consecutive clock pulse edges between set and reset transitions on said alternate third inverted clock pulse edges to provide symmetrical output pulses of frequency 1/3F with a substantially 50% duty cycle, said second means comprising logic means responsive directly to said clock pulses and to the output of said first flip-flop means for resetting said first flip-flop means every sixth clock pulse edge and for setting said first flip-flop means every third clock pulse edge following a reset clock pulse edge such that said flip-flop means is set every sixth clock pulse edge symmetrically interleaved with said resetting.

Claim 3

A divide by three digital clock divider circuit providing a symmetrical output, comprising: first flip-flop means for receiving clock pulses of frequency F; and second means for alternately setting and resetting said flip-flop means on alternate inverted third clock pulse edges, and for maintaining the set and reset states of said flip-flop means for two consecutive clock pulse edges between set and reset transitions on said alternate third inverted clock pulse edges to provide symmetrical output pulses of frequency 1/3F with a substantially 50% duty cycle, said second means comprising logic means responsive to said clock pulses and to the output of said first flip-flop means for resetting said first flip-flop means every sixth clock pulse edge and for setting said first flip-flop means every third clock pulse edge following a reset clock pulse edge such that said flip-flop means is set every sixth clock pulse edge symmetrically interleaved with said resetting wherein, second flip-flop means receives said clock pulses and the output of said first mentioned flip-flop means, and gate means receives said clock pulses and the output of said second flip-flop means, and outputs a reset signal to a reset input of said first flip-flop means, and outputs a set signal to a data input of said first flip-flop means for clocking therethrough by said clock pulses.

Claim 4

A divide by three digital clock divider circuit providing a symmetrical output, comprising: first flip-flop means for receiving clock pulses of frequency F; and second means for alternately setting and resetting said flip-flop means on alternate inverted third clock pulse edges, and for maintaining the set and reset states of said flip-flop means for two consecutive clock pulse edges between set and reset transitions on said alternate third inverted clock pulse edges to provide symmetrical output pulses of frequency 1/3F with a substantially 50% duty cycle, said second means comprising logic means responsive to said clock pulses and to the output of said first flip-flop means for resetting said first flip-flop means every sixth clock pulse edge and for setting said first flip-flop means every third clock pulse edge following a reset clock pulse edge such that said flip-flop means is set every sixth clock pulse edge symmetrically interleaved with said resetting wherein, second flip-flop means receives said clock pulses and the output of said first mentioned flip-flop means, and gate means receives said clock pulses and the output of said second flip-flop means, and outputs a reset signal to a reset input of said first flip-flop means, and outputs a set signal to a data input of said first flip-flop means for clocking therethrough by said clock pulses.

Claim 5

The invention according to claim 2 wherein: said first and second flip-flop means comprise first and second type D flip-flops each receiving said clock pulses at its C input; the output of said first flip-flop is connected to the D input of said second flip-flop; the output of said second flip-flop is connected to said gate means; the output of said gate means is connected to the R input and to the D input of said first flip-flop; and the output of said first flip-flop provides said symmetrical output pulses of frequency 1/3F.

Claim 6

The invention according to claim 3 wherein: the Q output of said first flip-flop is connected to the D input of said second flip-flop; the Q output of said second flip-flop is connected to said gate means; said gate means comprises a NOR gate receiving said clock pulses and said Q output of said second flip-flop; the output of said NOR gate is connected to the R input of said first flip-flop; and the output of said NOR gate is connected through an inverter to the D input of said first flip-flop.

Claim 7

A divide by three digital clock divider circuit providing a symmetrical output, comprising: a pair of flip-flops concurrently clocked by clock pulses of frequency F, the first flip-flop having an output connected to an input of the second flip-flop; and gate means receiving said clock pulses and an output of said second flip-flop, and delivering alternate control signals to said first flip-flop at every third clock pulse edge for alternately setting and resetting said first flip-flop on alternate inverted third clock pulse edges such that said output of said first flip-flop provides symmetrical pulses of frequency 1/3F with a substantially 50% duty cycle.

Claim 8

A divide by three digital clock divider circuit providing a symmetrical output, comprising: a pair of flip-flops concurrently clocked by clock pulses of frequency F, the first flip-flop having an output connected to an input of the second flip-flop; and gate means receiving said clock pulses and an output of said second flip-flop, and delivering alternate control signals to said first flip-flop at every third clock pulse edge for alternately setting and resetting said first flip-flop on alternate inverted third clock pulse edges such that said output of said first flip-flop provides symmetrical pulses of frequency 1/3F with a substantially 50% duty cycle.

Claim 9

The invention according to claim 5 wherein said output of said second flip-flop provides pulses of frequency 1/3F with a substantially 67% duty cycle, and the output of said gate means provides said reset control signal at frequency 1/3F with a substantially 17% duty cycle.

Claim 10

The invention according to claim 6 wherein the trailing pulse edge terminating the duty portion of a cycle of said reset control signal coincides with the leading pulse edge initiating the duty portion of a cycle of the signal from said output of said second flip-flop.

Claim 11

The invention according to claim 7 wherein the leading pulse edge initiating the duty portion of a cycle of said reset control signal coincides with the trailing pulse edge terminating the duty portion of a cycle of the signal from said output of said first flip-flop.

Claim 12

The invention according to claim 8 wherein: said leading pulse edge initiating the duty portion of a cycle of said reset control signal coincident with said trailing pulse edge terminating the duty portion of a cycle of the signal from said output of said first flip-flop is further coincident with a clock pulse edge of one polarity; and said trailing pulse edge terminating the duty portion of a cycle of said reset control signal coincident with said leading pulse edge initiating the duty portion of a cycle of the signal from said output of said second flip-flop is further coincident with the clock pulse edge immediately following said last mentioned clock pulse edge and of opposite polarity, such that the next leading pulse edge from said output of said first flip-flop initiating the duty portion of the next cycle therefrom is coincident with the next clock pulse edge of said opposite polarity.