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US4357656A
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Method and apparatus for disabling and diagnosing cache memory storage locations
Assignee: Digital Equipment Corp
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Filing: 1977-12-09
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Granted: 1982-11-02
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Expires: 1997-12-09
Abstract
Abstract In a data processing system having a main memory containing addressable main memory storage locations, and also having a processor with a cache memory containing addressable cache memory storage locations, signals representative of predetermined addressable cache memory storage locations desired to be intentionally disabled by an operator of the data processing system are compared with signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction. The data processing system is then caused to access the addressable main memory storage location when the signals representative of the predetermined addressable cache memory storage locations are in a predetermined fixed relationship with the signals representative of the addressable main memory storage location being addressed by the processor during the execution of the program instruction. When selected cache memory storage locations are thereby intentionally disabled, remaining enabled cache memory storage locations can be diagnosed by diagnostic program instructions which are loaded into main memory storage location by by-passing the selected cache memory storage locations. The enabled portions can then be tested by executing the diagnostic program instructions so loaded.
Inventors
- 👤 Warren L. Saltz
- 👤 Anthony S. Vezza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:43
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
305 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, said cache memory capable of comparing signals representative of address information indicative of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, a method for disabling predetermined ones of said plurality of addressable cache memory storage locations comprising the steps of: (a) generating signals representative of predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system; (b) comparing said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations with signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction; and (c) causing said data processing system to access said addressable main memory storage location being addressed by the processor during the execution of a program instruction when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location being addressed by the processor during execution of a program instruction, thereby intentionally disabling said predetermined ones of said plurality of addressable cache memory storage locations.
Claim 2
Dependent Claim
305 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, said cache memory capable of comparing signals representative of address information indicative of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, a method for disabling predetermined ones of said plurality of addressable cache memory storage locations comprising the steps of: (a) generating signals representative of predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system; (b) comparing said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations with signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction; and (c) causing said data processing system to access said addressable main memory storage location being addressed by the processor during the execution of a program instruction when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location being addressed by the processor during execution of a program instruction, thereby intentionally disabling said predetermined ones of said plurality of addressable cache memory storage locations.
Claim 3
Dependent Claim
275 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, each storage location identified by an index address, said cache memory capable of comparing signals representative of an address of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, a method for diagnosing the operation of addressable cache memory storage locations comprising the steps of: (a) intentionally disabling predetermined ones of said plurality of addressable cache memory storage locations, leaving remaining addressable cache memory storage locations desired to be diagnosed by an operator of the data processing system enabled; (b) creating diagnostic program instructions capable of being executed by said processor and having index addresses identifying said addressable cache memory storage locations desired to be diagnosed; (c) loading said diagnostic program instructions into ones of said plurality of addressable main memory storage locations by by-passing said disabled predetermined ones of said plurality of addressable cache memory storage locations; and (d) testing said enabled locations of said addressable cache memory storage locations by executing said diagnostic program instructions stored in said addressable plurality of main memory storage locations.
Claim 4
Dependent Claim
275 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, each storage location identified by an index address, said cache memory capable of comparing signals representative of an address of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, a method for diagnosing the operation of addressable cache memory storage locations comprising the steps of: (a) intentionally disabling predetermined ones of said plurality of addressable cache memory storage locations, leaving remaining addressable cache memory storage locations desired to be diagnosed by an operator of the data processing system enabled; (b) creating diagnostic program instructions capable of being executed by said processor and having index addresses identifying said addressable cache memory storage locations desired to be diagnosed; (c) loading said diagnostic program instructions into ones of said plurality of addressable main memory storage locations by by-passing said disabled predetermined ones of said plurality of addressable cache memory storage locations; and (d) testing said enabled locations of said addressable cache memory storage locations by executing said diagnostic program instructions stored in said addressable plurality of main memory storage locations.
Claim 5
Dependent Claim
187 words
The method for diagnosing the operation of addressable cache memory storage locations of claim 2 wherein the step of intentionally disabling predetermined addressable cache memory storage locations further comprises the steps of: (a) generating signals representative of predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system; (b) comparing said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations with signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction; and (c) causing said data processing system to access said addressable main memory storage location being addressed by the processor during the execution of a program instruction when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location addressed by the processor during execution of a program instruction, thereby intentionally disabling said predetermined ones of said plurality of addressable cache memory storage locations.
Claim 6
Dependent Claim
303 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, said cache memory also having hit/miss logic circuitry capable of comparing signals representative of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, cache control logic means for disabling predetermined ones of said plurality of addressable cache memory storage locations comprising: (a) means to generate signals representative of the predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system; and (b) signal comparison means, receptive of said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations and signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction, coupled to said cache memory hit/miss logic circuitry and capable of developing an output signal which causes said data processing system to access said addressable main memory storage location being addressed when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location being addressed by the processor during the execution of a program instruction.
Claim 7
Dependent Claim
303 words
In a data processing system having at least a main memory containing a plurality of addressable main memory storage locations and a processor for executing program instructions utilized to control the operation of the data processing system, said processor having a cache memory containing a plurality of addressable cache memory storage locations, said cache memory also having hit/miss logic circuitry capable of comparing signals representative of an addressable main memory storage location addressed by the processor during execution of a program instruction with signals representative of address information indicative of an addressable cache memory storage location addressed by the processor during the execution of a program instruction for determining whether the data processing system would access the addressable main memory storage location or would access the addressable cache memory storage location, cache control logic means for disabling predetermined ones of said plurality of addressable cache memory storage locations comprising: (a) means to generate signals representative of the predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system; and (b) signal comparison means, receptive of said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations and signals representative of an addressable main memory storage location being addressed by the processor during the execution of a program instruction, coupled to said cache memory hit/miss logic circuitry and capable of developing an output signal which causes said data processing system to access said addressable main memory storage location being addressed when said signals representative of said predetermined ones of said plurality of addressable cache memory storage locations are in a predetermined fixed relationship with said signals representative of the addressable main memory storage location being addressed by the processor during the execution of a program instruction.
Claim 8
Dependent Claim
79 words
The cache control logic means of claim 4 wherein said means to provide signals representative of predetermined ones of said plurality of addressable cache memory storage locations intentionally desired to be disabled by an operator of the data processing system comprises a register for storing digital information in response to defined program instructions executed by the processor whereby said digital information corresponds to the predetermined ones of said plurality of addressable cache memory storage locations desired to be disabled.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-01 | 1986-05-03 | 1986-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-01 | 1990-05-03 | 1990-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-01 | 1994-05-03 | 1994-11-02 | $7700.00 | Window Closed / Lapsed |