US4353032A
Expired / Lapsed
US
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Glitch detector
Assignee: Tektronix Inc
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Filing: 1980-06-02
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Granted: 1982-10-05
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Expires: 2000-06-02
Abstract
Abstract A glitch detector for use in a sampled data acquisition system is disclosed. Glitch detection is provided by a flip-flop which is set on a first signal transition, conditioning a logic gate, the output of which changes logic states on a second signal transition. Two such glitch detectors operatively associated with complementary data signals permits detection of either positive-going or negative-going glitches within a sample clock period. A glitch indication flip-flop is reset by a glitch detection signal, providing a glitch indication signal to an output terminal via a latch. Control and reset circuits are provided to facilitate glitch detection on every cycle of the sample clock, and at any point within a sample clock period.
Inventors
- 👤 Keith A. Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:54
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G06; G06F; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
93 words
A circuit for detecting two or more successive transitions of an input digital signal which occur within a clock period, comprising: first bistable circuit means for producing a changed logic state in response to the first of said two or more successive transitions of said input signal; means responsive to both said changed logic state and the second of said two or more successive transitions of said input signal for producing a detection signal; and second bistable circuit means responsive to said detection signal for producing a changed logic state indicating said detection.
Claim 2
Dependent Claim
93 words
A circuit for detecting two or more successive transitions of an input digital signal which occur within a clock period, comprising: first bistable circuit means for producing a changed logic state in response to the first of said two or more successive transitions of said input signal; means responsive to both said changed logic state and the second of said two or more successive transitions of said input signal for producing a detection signal; and second bistable circuit means responsive to said detection signal for producing a changed logic state indicating said detection.
Claim 3
Dependent Claim
48 words
A circuit in accordance with claim 1 further including means for providing the complement of said input signal, wherein said first bistable circuit means comprises a pair of flip-flops, one being responsive to said input signal and the other being responsive to the complement of said input signal.
Claim 4
Dependent Claim
41 words
A circuit in accordance with claim 2 further including means for providing a complementary control signal to enable one of said pair of flip-flops while disabling the other for said clock period, said control signal being derived from said input signal.
Claim 5
Dependent Claim
26 words
A circuit in accordance with claim 2 further including means for resetting said first and second bistable circuit means at the end of said clock period.
Claim 6
Dependent Claim
54 words
A circuit in accordance with claim 4 wherein said resetting means includes a flip-flop triggerable at the end of said clock period, the output of said flip-flop being connected to said second bistable circuit means to cause said second bistable means to revert from said changed logic state to a first bistable logic state.
Claim 7
Dependent Claim
94 words
In a sampled data acquisition system, a circuit for detecting glitches occurring within a sample clock period, comprising: signal input means including a data latch which is periodically updated under sample clock control with the logic state of the input signal; detector circuit means for producing a detection signal if two or more successive transitions of the input signal occur within the sample clock period, said detector circuit means comprising in combination a flip-flop and a logic gate; and glitch indication circuit means responsive to said detection signal for producing a glitch indication signal.
Claim 8
Dependent Claim
94 words
In a sampled data acquisition system, a circuit for detecting glitches occurring within a sample clock period, comprising: signal input means including a data latch which is periodically updated under sample clock control with the logic state of the input signal; detector circuit means for producing a detection signal if two or more successive transitions of the input signal occur within the sample clock period, said detector circuit means comprising in combination a flip-flop and a logic gate; and glitch indication circuit means responsive to said detection signal for producing a glitch indication signal.
Claim 9
Dependent Claim
37 words
A glitch detector circuit in accordance with claim 6 wherein said detector circuit means further comprises a second combination of a flip-flop and a logic gate so that detection of both positive-going and negative-going glitches is facilitated.
Claim 10
Dependent Claim
38 words
A glitch detector circuit in accordance with claim 6 further including means for resetting said detector circuit means and said glitch indication circuit means such that glitch detection may be provided on every cycle of said sample clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-04 | 1986-04-05 | 1986-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-04 | 1990-04-05 | 1990-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-04 | 1994-04-05 | 1994-10-05 | $7700.00 | Window Closed / Lapsed |