US4070631A
Expired / Lapsed
US
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Digital noise blanking circuit
Assignee: Motorola Solutions Inc
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Filing: 1976-11-26
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Granted: 1978-01-24
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Expires: 1996-11-26
Abstract
Abstract A digital noise blanking circuit for use in generating a single output pulse in response to a noisy signal which may include clusters of noise-induced pulses, the circuit utilizing a digital counter which is operated for a preset period of time longer than the time during which noise-induced transitional pulses may occur.
Inventors
- 👤 Harold Garth Nash
- 👤 Jack Whitmore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/069; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
90 words
A digital noise blanking circuit for converting a noisy time domain input signal into a series of transitional pulses comprising: a. first means for converting the zero axis crossings of the noisy input signal into clusters of transitional pulses, b. second means for generating a single transitional pulse for each of the clusters of transitional pulses, c. said second means including: 1. logic circuit means; and 2. N-stage counter means coupled to said logic circuit means for generating a single transitional pulse in response to each cluster of transitional pulses.
Claim 2
Dependent Claim
90 words
A digital noise blanking circuit for converting a noisy time domain input signal into a series of transitional pulses comprising: a. first means for converting the zero axis crossings of the noisy input signal into clusters of transitional pulses, b. second means for generating a single transitional pulse for each of the clusters of transitional pulses, c. said second means including: 1. logic circuit means; and 2. N-stage counter means coupled to said logic circuit means for generating a single transitional pulse in response to each cluster of transitional pulses.
Claim 3
Dependent Claim
46 words
A digital noise blanking circuit for converting a noisy time domain input signal into a series of transitional pulses according to claim 1 wherein: a. said logic circuit means includes a latch; b. said n-stage counter means includes means for selectively resetting said logic circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-23 | 1981-07-25 | 1982-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-23 | 1985-07-25 | 1986-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-23 | 1989-07-25 | 1990-01-24 | $7700.00 | Window Closed / Lapsed |