US3958133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital noise discriminator
Assignee: RTX Corp
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Filing: 1975-03-03
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Granted: 1976-05-18
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Expires: 1995-03-03
Abstract
Abstract A digital circuit discriminates between valid transitions in the level of a two level logic signal in which the signal remains at its new level for a predetermined time period, and those transitions in the level of the logic signal which may be caused by noise. Upon the transition of the logic signal from one level to another, a timer is actuated. If the logic signal remains in its new level until the timer expires, the transition is considered valid and an output signal indicative thereof is produced. If the logic signal reverts to its initial level before the timer expires, the transition is considered invalid, the timer is reset and no output signal is produced. A discrete output is produced when a valid transition occurs between either of the two separate logic signal levels.
Inventors
- 👤 Rocco V. Albano
- 👤 Robert J. Fraleigh
- 👤 Jack E. Steffens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:32
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273; H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; H03K5/00; H03K5/01; H03K5/125; H03K5/1252; H04; H04B; H04B1/00; H04B1/06; H04B1/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
Apparatus for indicating a transition in a two level logic signal from one of said two levels to the other of said levels which remains at the other level for a selected time period, comprising a flip flop connected to receive said logic signal as an input thereto, means responsive to a transition in the signal level of said logic signal from a first level to a second level for producing a change in the output state of said flip flop, a timing means having a preselected timing period, means responsive to a change in the output state of said flip flop for actuating said timing means, means for resetting said timing means upon a transition in said logic signal from said second level to said first level during the time that said timing means is actuated, means responsive to the timing out of said timing means for producing a first output signal, means including said flip flop responsive to a transition in said logic signal from said second level to saif first level for actuating said timing means, means for resetting said timing means upon a transition in said logic signal from said first level to said second level during the time that said timing means is actuated, and means responsive to the timing out of said timing means for producing a second output signal.
Claim 2
Dependent Claim
226 words
Apparatus for indicating a transition in a two level logic signal from one of said two levels to the other of said levels which remains at the other level for a selected time period, comprising a flip flop connected to receive said logic signal as an input thereto, means responsive to a transition in the signal level of said logic signal from a first level to a second level for producing a change in the output state of said flip flop, a timing means having a preselected timing period, means responsive to a change in the output state of said flip flop for actuating said timing means, means for resetting said timing means upon a transition in said logic signal from said second level to said first level during the time that said timing means is actuated, means responsive to the timing out of said timing means for producing a first output signal, means including said flip flop responsive to a transition in said logic signal from said second level to saif first level for actuating said timing means, means for resetting said timing means upon a transition in said logic signal from said first level to said second level during the time that said timing means is actuated, and means responsive to the timing out of said timing means for producing a second output signal.
Claim 3
Dependent Claim
14 words
Apparatus as in claim 1 in which said timing means is a digital counter.
Claim 4
Dependent Claim
14 words
Apparatus as in claim 1 in which said timing means is a monostable multivibrator.
Claim 5
Independent Claim
179 words
A method for indicating a transition in a two level logic signal from one of said two levels to the other of said levels which remains at the other level for a selected time period, comprising sensing the occurrence of a transition in said logic signal, actuating a timing mechanism upon the occurrence of a transition in said logic signal from a first level to a second level, said timing mechanism having a predetermined timing period, resetting said timing mechanism upon the occurrence of a transition in said logic signal from said second level to said first level before expiration of said predetermined timing period, producing a first output signal upon expiration of said timing period, actuating said timing mechanism upon the occurrence of a transition in said logic signal from said second level to said first level, resetting said timing mechanism upon the occurrence of a transition in said logic signal from said first level to said second level before expiration of said predetermined timing period, and producing a second output signal upon expiration of said timing period.
Claim 6
Independent Claim
179 words
A method for indicating a transition in a two level logic signal from one of said two levels to the other of said levels which remains at the other level for a selected time period, comprising sensing the occurrence of a transition in said logic signal, actuating a timing mechanism upon the occurrence of a transition in said logic signal from a first level to a second level, said timing mechanism having a predetermined timing period, resetting said timing mechanism upon the occurrence of a transition in said logic signal from said second level to said first level before expiration of said predetermined timing period, producing a first output signal upon expiration of said timing period, actuating said timing mechanism upon the occurrence of a transition in said logic signal from said second level to said first level, resetting said timing mechanism upon the occurrence of a transition in said logic signal from said first level to said second level before expiration of said predetermined timing period, and producing a second output signal upon expiration of said timing period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-18 | 1979-11-17 | 1980-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-18 | 1983-11-17 | 1984-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-18 | 1987-11-17 | 1988-05-18 | $7700.00 | Window Closed / Lapsed |