US3727142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse stream noise discriminator
Assignee: United States Department of the Navy
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Filing: 1968-12-02
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Granted: 1973-04-10
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Expires: 1988-12-02
Abstract
Abstract An apparatus for determining the quality of an input data pulse stream by continuously monitoring each respective pulse thereof for a specified duration. The data pulses are rejected as noise if the duration thereof is less than that of a desired signal and the apparatus provides lock out and clear signals to prevent the data from being processed. If a valid data pulse stream is detected, a clock signal is developed which functions, through other circuitry, to enable a sequence register to accept this data and clock it into appropriate flip-flops therein. In addition, an inhibit signal is developed to prevent the reception of any signals during the processing of the valid data pulse stream. An automatic/manual read control unit functions to clear and then enable a display to read the valid data pulse stream temporarily stored in the sequence register.
Inventors
- 👤 Sipio R De
- 👤 T Long
- 👤 H Beyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:39
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
150 words
A noise discriminator, comprising: data insert means receiving an input data pulse stream and providing an output replica thereof in the absence of the receipt of an inhibiting signal; first means operatively connected to receive said replica for providing a first series of pulses of predetermined duration and a second series of pulses of like predetermined duration, said first series of pulses and said second series of pulses being of opposite polarity; monitoring means operatively connected to receive said replica and said first series of pulses for monitoring each pulse of said replica for predetermined time periods and providing a signal indicative of a noise condition if any of said replica pulses chAnges state during said monitoring time periods; and logic circuit means operatively connected to receive said signal indicative of a noise condition and said second series of pulses for providing an inhibitory signal to said data insert means.
Claim 2
Dependent Claim
150 words
A noise discriminator, comprising: data insert means receiving an input data pulse stream and providing an output replica thereof in the absence of the receipt of an inhibiting signal; first means operatively connected to receive said replica for providing a first series of pulses of predetermined duration and a second series of pulses of like predetermined duration, said first series of pulses and said second series of pulses being of opposite polarity; monitoring means operatively connected to receive said replica and said first series of pulses for monitoring each pulse of said replica for predetermined time periods and providing a signal indicative of a noise condition if any of said replica pulses chAnges state during said monitoring time periods; and logic circuit means operatively connected to receive said signal indicative of a noise condition and said second series of pulses for providing an inhibitory signal to said data insert means.
Claim 3
Dependent Claim
109 words
A noise discriminator according to claim 1, wherein: said first means comprises first timing means and an inverting means operatively connected thereto; said first series of pulses are provided by said timing means as a first series of positive going pulses; said second series of pulses are provided by said timing means and are negative going pulses, whereby said inverting means inverts said negative going pulses to thereby provide a second series of positive going pulses; and said monitoring means comprises a first logic gate operatively connected to said first timing means and receiving therefrom said first series of positive going pulses for monitoring said replica pulses received thereby.
Claim 4
Dependent Claim
70 words
A noise discriminator according to claim 2, wherein said data insert means comprises: a second logic gate receiving said input data pulse stream; and a third logic gate having at least two input terminals operatively connected at one of the input terminals thereof to the output of said second logic gate for providing said replica in the absence of receiving the inhibitory signal at the other of said input terminals.
Claim 5
Dependent Claim
60 words
A noise discriminator according to claim 3, wherein said logic circuit means comprises: second timing means operatively connected to the output of said inverting means for providing clock pulses responsive thereto; and a fourth logic gate having at least two input terminals and operatively connected at one input terminal thereof to said second timing means for inverting said clock pulses.
Claim 6
Dependent Claim
67 words
A noise discriminator according to claim 4, wherein said logic circuit means further comprises: third timing means operatively connected to the output of said fourth logic gate for providing a timing pulse responsive to the receipt of the first of said inverted clock pulses; and a fifth logic gate operatively connected to said third timing means and responsive to said timing pulse for providing an enable signal.
Claim 7
Dependent Claim
38 words
A noise discriminator according to claim 5, wherein: said fifth logic gate is further operatively connected to said first logic gate for providing a clear signal responsive to the receipt of said signal indicative of a noise condition.
Claim 8
Dependent Claim
77 words
A noise discriminator according to claim 6, wherein said logic circuit means further comprises: a sixth logic gate operatively connected to said first logic gate and said fourth logic gate for providing an energizing pulse responsive, respectively, to the receipt of said signal indicative of a noise condition or said inverted clock pulses; and fourth timing means for providing said inhibitory signal to said third logic gate in response to the receipt thereto of said energizing pulse.
Claim 9
Dependent Claim
119 words
A noise discriminator according to claim 7, wherein said logic circuit means further comprises: a seventh logic gate for providing a clear pulse upon the coincidence of like state logic input signals supplied to the input terminals thereof; flip-flop means receiving said inverted clock pulses and operatively connected to said seventh logic gate for supplying a logic input signal to one of the inputs thereof; an eighth logic gate receiving said timing pulse from said third timing means and providing an output pulse upon the coincidence of the receipt thereto of at least another pulse of like logic state as said timing pulse; and a ninth logic gate receiving said output pulse and providing a read pulse responsive thereto.
Claim 10
Dependent Claim
37 words
A noise discriminator according to claim 8, wherein: said eighth logic gate further provides said output pulse upon the coincidence of like state logic input pulses supplied thereto to said flip-flop means to change the state thereof.
Claim 11
Dependent Claim
102 words
A noise discriminator accorDing to claim 9, further comprising: sequence register means simultaneously providing a pulse indicative of a full register condition to said seventh logic gate and said eighth logic gate; means providing a control logic signal of a first logic state to said seventh logic gate and a like control logic signal of a second logic state to said eighth logic gate, said eighth logic gate providing said output pulse when said first logic state is the same as that of said pulse indicative of a full register condition and that of said timing pulse from said third timing means.
Claim 12
Dependent Claim
41 words
A noise discriminator according to claim 10, wherein: said seventh logic gate provides said clear pulse when said second logic state is the same as that of said logic input signal and that of said pulse from said sequence register means.
Claim 13
Dependent Claim
33 words
A noise discriminator according to claim 11, further comprising: means connected to said third logic gate for inhibiting said gate responsive to the receipt of said pulse indicative of a full register condition.
Claim 14
Dependent Claim
35 words
A noise discriminator according to claim 12, further comprising: means for supplying a signal to said ninth logic gate which, responsive thereto, provides said read pulse irrespective of the presence or absence of other signals.
Claim 15
Dependent Claim
65 words
A noise discriminator according to claim 13, further comprising: manual means supplying a signal to said seventh logic gate to inhibit said gate from providing said clear pulse for an externally determined time period; and means connected to the output of said seventh logic gate for providing yet another clear pulse irrespective of the presence or absence of signals supplied to said seventh logic gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |