US3593162A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog comparator
Assignee: Electronic Associates Inc
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Filing: 1969-03-25
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Granted: 1971-07-13
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Expires: 1989-03-25
Abstract
Abstract A circuit arrangement for eliminating noise-generated ambiguous outputs of an analog comparator is disclosed providing a number of flip-flops operating in the shift register mode resulting in a pulse width discrimination of the comparator output directly proportional to the number of flip-flops.
Inventors
- 👤 James R Patmore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:59
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
105 words
A circuit for eliminating the effects of noise-generated outputs from a comparison means comprising: comparison means for producing an output pulse whenever the sum of the input signals thereto changes sign, and pulse width discrimination means including a plurality of flipflops Connected to said comparison means having at least a first and a last flip-flop; a logical AND gate having inputs connected to the outputs of said first and last flip-flops, and a source of clock pulses connected to each of said flip-flops for producing an output indication if said output pulse duration is greater than a duration dependent upon the number of said flip-flops.
Claim 2
Dependent Claim
105 words
A circuit for eliminating the effects of noise-generated outputs from a comparison means comprising: comparison means for producing an output pulse whenever the sum of the input signals thereto changes sign, and pulse width discrimination means including a plurality of flipflops Connected to said comparison means having at least a first and a last flip-flop; a logical AND gate having inputs connected to the outputs of said first and last flip-flops, and a source of clock pulses connected to each of said flip-flops for producing an output indication if said output pulse duration is greater than a duration dependent upon the number of said flip-flops.
Claim 3
Dependent Claim
181 words
A circuit for eliminating noise-generated outputs of a comparison means comprising: comparison means for producing an output indication whenever the sum of the input signals thereto changes sign, a plurality of ''''JK'''' flip-flops operating in the shift register mode including a first and a last flip-flop, each of said flip-flops having set, trigger and clear input terminals and ONE and ZERO output terminals, for propagating ONE and ZERO output signals from said first to said last flip-flop, means connected to said comparison means and to said first set input terminal for applying said output indication to said first set terminal, inversion means having an input connected to said comparison means and an output connected to said first clear terminal, a source of clock pulses connected to each of said trigger input terminals so that occurrence of an output indication and a clock pulse produce ONE and ZERO output at said first flip-flop, and a logical AND gate having inputs connected to said first and last ONE output terminals for producing an output when said inputs thereto are in a ONE state.
Claim 4
Dependent Claim
181 words
A circuit for eliminating noise-generated outputs of a comparison means comprising: comparison means for producing an output indication whenever the sum of the input signals thereto changes sign, a plurality of ''''JK'''' flip-flops operating in the shift register mode including a first and a last flip-flop, each of said flip-flops having set, trigger and clear input terminals and ONE and ZERO output terminals, for propagating ONE and ZERO output signals from said first to said last flip-flop, means connected to said comparison means and to said first set input terminal for applying said output indication to said first set terminal, inversion means having an input connected to said comparison means and an output connected to said first clear terminal, a source of clock pulses connected to each of said trigger input terminals so that occurrence of an output indication and a clock pulse produce ONE and ZERO output at said first flip-flop, and a logical AND gate having inputs connected to said first and last ONE output terminals for producing an output when said inputs thereto are in a ONE state.
References Cited (Backward Citations)
US3395353A
Cited
US3513400A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-12 | 1975-01-11 | 1975-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-12 | 1979-01-11 | 1979-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-12 | 1983-01-11 | 1983-07-13 | $7700.00 | Window Closed / Lapsed |