Patent US4320527A successfully refreshed from Google Patents.
US4320527A
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Bit synchronizing system for pulse signal transmission
Assignee: Hitachi Ltd
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Filing: 1979-08-15
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Granted: 1982-03-16
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Expires: 1999-08-15
Abstract
Abstract A bit synchronizing system for generating a timing signal corresponding to a transmitted pulse signal is disclosed in which the transmitted pulse signal is converted into a signal in which the number of pulses successively assuming the same polarity is limited to permit detection of frequency, the converted signal is integrated, a peak of integrated values is detected, the output of a voltage-controlled clock generator for generating the timing signal is processed in a similar manner to detect a peak with respect to the output, and the clock generator is controlled by a voltage corresponding to a difference between these two peaks, whereby the frequency of clock signal coincides with the bit rate of the transmitted pulse signal.
Inventors
- 👤 Yoshitaka Takasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:42
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0054; H04L7/007; H04L7/04; H04L7/041
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
164 words
A bit synchronizing system for a pulse signal transmission comprising: an input terminal to which a transmitted pulse signal is applied, said pulse signal being coded by a restricted code whose pulse repetition frequency is detectable; a clock signal generator, the output frequency thereof being variable in response to a voltage applied thereto; a first circuit for converting said pulse signal from the input terminal into a signal proportional to the frequency of said pulse signal from the input terminal; a second circuit for converting the output pulse of said clock signal generator into a signal proportional to the frequency of said output pulse of said clock signal generator; a comparing circuit for generating a signal corresponding to the difference between respective outputs of said first and second circuits; means for controlling the frequency of said clock signal generator by means of the output of said comparing circuit; and means for taking out the output of said clock signal generator as a timing signal.
Claim 2
Dependent Claim
164 words
A bit synchronizing system for a pulse signal transmission comprising: an input terminal to which a transmitted pulse signal is applied, said pulse signal being coded by a restricted code whose pulse repetition frequency is detectable; a clock signal generator, the output frequency thereof being variable in response to a voltage applied thereto; a first circuit for converting said pulse signal from the input terminal into a signal proportional to the frequency of said pulse signal from the input terminal; a second circuit for converting the output pulse of said clock signal generator into a signal proportional to the frequency of said output pulse of said clock signal generator; a comparing circuit for generating a signal corresponding to the difference between respective outputs of said first and second circuits; means for controlling the frequency of said clock signal generator by means of the output of said comparing circuit; and means for taking out the output of said clock signal generator as a timing signal.
Claim 3
Dependent Claim
63 words
A bit synchronizing system according to claim 1, wherein said transmitted pulse signal is a signal in which the number of pulses successively assuming the same polarity is limited, and wherein each of said first and second circuits include a circuit for integrating an input pulse and for detecting a maximum value obtained by said integration to obtain signals proportional to the frequencies.
Claim 4
Dependent Claim
30 words
A bit synchronizing system according to claim 2, wherein said transmitted pulse signal, in which the number of pulses successively assuming the same polarity is limited, is a dc-balanced signal.
Claim 5
Dependent Claim
162 words
A bit synchronizing system according to claim 2, wherein said transmitted pulse signal, in which the number of pulses successively assuming the same polarity is limited, has a waveform such that a code pulse of the polarity of "1" or "0" having a predetermined pulse width is generated for each of the states of "1" in said transmitted pulse signal in such a manner that said code pulse of the polarity of "1" and said code pulse of the polarity of "0" are alternately generated, a combination of a code pulse of the polarity of "1" and a code pulse of the polarity of "0" each having a pulse width equal to one-half of said predetermined pulse width is generated for each of the states of "0" in said transmitted pulse signal, and all code pulses are arranged in such a manner that a code pulse of the polarity of "1" and a code pulse of the polarity of "0" alternately appear.
Claim 6
Dependent Claim
162 words
A bit synchronizing system according to claim 2, wherein said transmitted pulse signal, in which the number of pulses successively assuming the same polarity is limited, has a waveform such that a code pulse of the polarity of "1" or "0" having a predetermined pulse width is generated for each of the states of "0" in said transmitted pulse signal in such a manner that said code pulse of the polarity of "1" and said code pulse of the polarity of "0" are alternately generated, a combination of a code pulse of the polarity of "1" and a code pulse of the polarity of "0" each having a pulse width equal to one-half of said predetermined pulse width is generated for each of the states of "1" in said transmitted pulse signal, and all code pulses are arranged in such a manner that a code pulse of the polarity of "1" and a code pulse of the polarity of "0" alternately appear.
Claim 7
Dependent Claim
62 words
A bit synchronizing system according to claim 1, wherein each of said first and second circuits includes a circuit for detecting transitions contained in an input pulse and a circuit for counting said detected transitions, and wherein said comparing circuit compares a counted value of transitions outputted from said first circuit with a counted value of transitions outputted from said second circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-15 | 1985-09-14 | 1986-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-15 | 1989-09-14 | 1990-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-15 | 1993-09-14 | 1994-03-16 | $7700.00 | Window Closed / Lapsed |