Digital phase shifter/synchronizer and method of shifting

Claim 2

A synchronizer, having a clock producing clock pulses, for synchronizing electronic input pulses of an input pulse train with the clock pulses, comprising: a. input means, for receiving the input pulses; b. reference pulse generating means, operatively connected to the clock and to the input means, for producing reference pulses, phase-shifted by 1/2 of 1 clock cycle in one direction; c. indicating means, receiving the reference pulses, for providing an indicator signal when a first predetermined condition is reached to selectively invert the reference pulses for phase-shifting by 1/2 of 1 clock cycle in the other direction; and d. output means, connected to the indicating means, for providing a sampling signal when a second predetermined condition is reached.

Claim 3

The synchronizer of claim 1, further comprising; e. inhibit means, responsive to the indicating means operatively connected to permit the reference pulse generating means to produce electronic pulses in phase with the clock pulses when the inhibit means are activated.

Claim 4

The synchronizer of claim 1 wherein the indicating means further comprise pulse counting means and provide the indicator signal when a predetermined count is reached.

Claim 5

The synchronizer of claim 2 wherein the indicating means further comprise pulse counting means and provide the indicator signal when a predetermined count is reached.

Claim 6

The synchronizer of claim 1 wherein the reference pulse generating means further comprise: d. i. phase shifting means for reproducing the clock pulses, selectively shifted by 1/2 cycle in one direction; ii. monitoring means, responsive to the indicating means and having a selectively activated output; iii. divider means, electrically connected to the phase shifting means for dividing the reproduced clock pulse by 2, and having a reference pulse output at 1/2 of the clock frequency, shifted by 1/2 of 1 clock cycle in the one direction and serving as an input to the indicating means; and iv. logic means, responsive to the output of the monitoring means and to the divider means to permit the reference pulses to be unaffected when the monitoring means output is not activated, and to shift the reference pulses by a full clock cycle in the other direction when the monitoring means output is activated, thereby affecting a net 1/2 clock cycle phase shift of the reference pulses in the other direction.

Claim 7

The synchronizer of claim 2 wherein the reference pulse generating means further comprise: d. i. phase shifting means for reproducing the clock pulses, selectively shifted by 1/2 cycle in one direction; ii. monitoring means, responsive to the indicating means and having a selectively activated output; iii. divider means, electrically connected to the phase shifting means for dividing the reproduced clock pulse by 2, and having a reference pulse output at 1/2 of the clock frequency, shifted by 1/2 of 1 clock cycle in the one direction and serving as an input to the indicating means; and iv. logic means, responsive to the output of the monitoring means and to the divider means to permit the reference pulses to be unaffected when the monitoring means output is not activated, and to shift the reference pulses by a full clock cycle in the other direction when the monitoring means output is activated, thereby affecting a net 1/2 clock cycle phase shift of the reference pulses in the other direction.

Claim 8

The synchronizer of claim 6 wherein the inhibit means further comprise: e. i. decoder means, electrically connected and responsive to the indicating means, for providing an output signal when a third predetermined condition has been reached in the indicating means; and ii. gating means, operatively connected to the phase shifting means, and responsive to the decoder means output to cause the phase shifting means to shift the reproduced clock pulse waveform by 1/2 of 1 clock cycle in the one direction.

Claim 9

An electronic synchronizer for synchronizing the pulse rate of the waveform of an internal clock of an electronic system with the pulse rate of an input pulse train representative of digital data, comprising: a. input means for receiving the data pulses; b. clock input means, for receiving the clock pulses; c. phase-shifting means, electrically connected to the input means and the clock input means for reproducing the clock waveform, phase-shifted 1/2 of 1 clock cycle in one direction; d. combining means, electrically connected to the phase-shifting means, for producing a reference pulse waveform at 1/2 the pulse rate of the clock waveform, selectively phase-shifted by 1/2 of 1 clock cycle in the one direction or in the other direction; e. indicating means, for receiving the reference pulses from the combining means and for providing an indicator signal when a predetermined condition is reached; f. monitoring means, responsive to the phase-shifting means, for monitoring the indicating means, and electrically connected to the combining means to permit a phase shift of 1/2 of 1 clock cycle in the one direction in the absence of an indicator signal and to permit a phase shift of 1/2 of 1 clock cycle in the other direction in the presence of an indicator signal; and g. output means, electrically connected to the indicating means, to provide a sampling signal to the electronic system when a predetermined condition is reached.

Claim 10

An electronic synchronizer for synchronizing the pulse rate of the waveform of an internal clock of an electronic system with the pulse rate of an input pulse train representative of digital data, comprising: a. input means for receiving the data pulses; b. clock input means, for receiving the clock pulses; c. phase-shifting means, electrically connected to the input means and the clock input means for reproducing the clock waveform, phase-shifted 1/2 of 1 clock cycle in one direction; d. combining means, electrically connected to the phase-shifting means, for producing a reference pulse waveform at 1/2 the pulse rate of the clock waveform, selectively phase-shifted by 1/2 of 1 clock cycle in the one direction or in the other direction; e. indicating means, for receiving the reference pulses from the combining means and for providing an indicator signal when a predetermined condition is reached; f. monitoring means, responsive to the phase-shifting means, for monitoring the indicating means, and electrically connected to the combining means to permit a phase shift of 1/2 of 1 clock cycle in the one direction in the absence of an indicator signal and to permit a phase shift of 1/2 of 1 clock cycle in the other direction in the presence of an indicator signal; and g. output means, electrically connected to the indicating means, to provide a sampling signal to the electronic system when a predetermined condition is reached.

Claim 11

The synchronizer of claim 8 wherein the indicating means further comprise a counter, providing the indicator signal when a predetermined count is reached.

Claim 12

The synchronizer of claim 9 wherein the clock input means further comprise inverting means to receive the clock waveform, designated CLK, and to provide an inverted clock waveform designated CLK.

Claim 13

The synchronizer of claim 10 wherein the phase shifting means further comprise: c. i. first bi-stable means, responsive to the input means and to the clock waveform, and having an output designated B and an output designated B; ii. second bi-stable means, responsive to the first bi-stable means and to the inverted clock waveform, having an output designated C and an output designated C; and iii. a logic array, providing the logic output: CLK.C + CLK.B.

Claim 14

The synchronizer of claim 11 wherein the combining means further comprise: d. i. third bi-stable means, responsive to the output of the phase-shifting means, to provide a waveform that is 1/2 the frequency of the output waveform of the phase-shifting means; and ii. first logic means, having an input from the third bi-stable means and an input from the monitoring means, for providing an output waveform at the same frequency and in phase with the waveform output of the third bi-stable means in the absence of an indicator signal, and for providing an output waveform at the same frequency and phase-shifted one clock cycle in the other direction with respect to the waveform output of the third bi-stable means.

Claim 15

The synchronizer of claim 11 wherein the monitoring means further comprise: f. i. fourth bi-stable means having an output connected to the combining means; ii. Second logic means, having the indicator signal as an input and having an output from the fourth bi-stable means as an input, to condition the fourth bi-stable means to change from one bi-stable state to the other bi-stable state; and iii. third logic means having one input from the first bi-stable means and second input from the third bi-stable means, providing logic output: B.C + B.C, operatively connected to cause the fourth bi-stable means to change from one bi-stable state to the other bi-stable state in the presence of the indicator signal.

Claim 16

The synchronizer of claim 12 wherein the monitoring means further comprise: f. i. fourth bi-stable means having an output connected to the combining means; ii. second logic means, having the indicator signal as an input and having an output from the fourth bi-stable means as an input, to condition the fourth bi-stable means to change from one bistable state to the other bi-stable state; and iii. third logic means having one input from the first bi-stable means and second input from the third bi-stable means, providing logic output: B.C + B.C operatively connected to cause the fourth bi-stable means to change from one bi-stable state to the other bi-stable state in the presence of the indicator signal.

Claim 17

The synchronizer of claim 14 wherein the output means are connected to the counter to monitor the state of the most significant bit of the counter.

Claim 18

An electronic synchronizer for synchronizing the pulse rate of the waveform of an internal clock of an electronic system with the pulse rate of an input pulse train representative of digital data, comprising: a. input means for receiving the data pulses; b. clock input means, for receiving the clock pulses; c. phase-shifting means, electrically connected to the input means and the clock input means for reproducing the clock waveform, selectively phase-shifted 1/2 of 1 clock cycle in one direction; d. combining means, electrically connected to the phase shifting means, for producing a reference pulse waveform at 1/2 the pulse rate of the clock waveform, selectively phase-shifted by 1/2 of 1 clock cycle in thE one direction or in the other direction; e. indicating means, for receiving the reference pulses from the combining means and for providing an indicator signal when a predetermined condition is reached; f. monitoring means, for monitoring the indicating means and electrically connected to the combining means to selectively permit a phase-shift of one-half of 1 clock cycle in the one direction in the absence of an indicator signal and to permit a phase-shift of one-half of 1 clock cycle in the other direction in the presence of an indicator signal; g. decoding means, operatively connected to the indicating means to provide an inhibit signal to the input means representative of a second predetermined condition of the indicating means; h. inhibit means, operatively connected to the phase shifting means to prevent a phase shift in the presence of an inhibit signal and to permit a phase shift in the absence of an inhibit signal; i. disabling means, operatively connected to disable the monitoring means in the presence of an inhibit signal; and j. output means, electrically connected to the indicating means, to provide a sampling signal to the electronic system when a predetermined condition is reached.

Claim 19

An electronic synchronizer for synchronizing the pulse rate of the waveform of an internal clock of an electronic system with the pulse rate of an input pulse train representative of digital data, comprising: a. input means for receiving the data pulses; b. clock input means, for receiving the clock pulses; c. phase-shifting means, electrically connected to the input means and the clock input means for reproducing the clock waveform, selectively phase-shifted 1/2 of 1 clock cycle in one direction; d. combining means, electrically connected to the phase shifting means, for producing a reference pulse waveform at 1/2 the pulse rate of the clock waveform, selectively phase-shifted by 1/2 of 1 clock cycle in thE one direction or in the other direction; e. indicating means, for receiving the reference pulses from the combining means and for providing an indicator signal when a predetermined condition is reached; f. monitoring means, for monitoring the indicating means and electrically connected to the combining means to selectively permit a phase-shift of one-half of 1 clock cycle in the one direction in the absence of an indicator signal and to permit a phase-shift of one-half of 1 clock cycle in the other direction in the presence of an indicator signal; g. decoding means, operatively connected to the indicating means to provide an inhibit signal to the input means representative of a second predetermined condition of the indicating means; h. inhibit means, operatively connected to the phase shifting means to prevent a phase shift in the presence of an inhibit signal and to permit a phase shift in the absence of an inhibit signal; i. disabling means, operatively connected to disable the monitoring means in the presence of an inhibit signal; and j. output means, electrically connected to the indicating means, to provide a sampling signal to the electronic system when a predetermined condition is reached.

Claim 20

The synchronizer of claim 16 wherein the indicating means further comprise a counter, providing the indicator signal when a predetermined count is reached.

Claim 21

The synchronizer of claim 17 wherein the clock input means further comprise inverting means to receive the clock waveform, designated CLK, and to provide an inverted clock waveform designated CLK.

Claim 22

The synchronizer of claim 18 wherein the phase-shifting means further comprise: C. i. first bi-stable means, responsive to the input means and the clock waveform, and having an output designated B and an output designated B; ii. second bi-stable means, responsive to the first bi-stable means and to the inverted clock waveform, having an output designated C and an output designated C; and iii. a logic array, providing the logic output: CLK.C + CLK.B.

Claim 23

The synchronizer of claim 19 wherein the combining means further comprise: d. i. third bi-stable means, responsive to the output of the phase-shifting means, to provide a waveform that is one half the frequency of the output waveform of the phase-shifting means; and ii. first logic means, having an input from the third bi-stable means and an input from the monitoring means, for providing an ouput waveform at the same frequency and in phase with the waveform output of the third bi-stable means in the absence of an indicator signal, and for providing an output waveform at the same frequency and phase-shifted one clock cycle in the other direction with respect to the waveform output of the third bi-stable means.

Claim 24

The synchronizer of claim 19 wherein the monitoring means further comprise: f. i. fourth bi-stable means having an output connected to the combining means; ii. second logic means, having the indicator signal as an input and having an output from the fourth bi-stable means as an input, to condition the fourth bi-stable means to change from one bi-stable state to the other bi-stable state; and iii. third logic means having one input from the first bi-stable means and second input from the third bi-stable means, providing logic output: B.C + B.C, operatively connected to cause the fourth bi-stable means to change from one bi-stable state to the other bi-stable state in the presence of the indicator signal.

Claim 25

The synchronizer of claim 21 wherein the monitoring means further comprise: f. i. fourth bi-stable means having an output connected to the combining means; ii. second logic means, having the indicator signal as an input and having an output from the fourth bi-stable means as an input, to condition the fourth bi-stable means to change from one bi-stable state to the other bi-stablE state; and iii. third logic means having one input from the first bi-stable means and second input from the third bi-stable means, providing logic output: B.C + B.C, operatively connected to cause the fourth bi-stable means to change from one bi-stable state to the other bi-stable state in the presence of the indicator signal.

Claim 26

The synchronizer of claim 22 wherein the output means are connected to the counter to monitor the state of the most significant bit of the counter.

Claim 27

The synchronizer of claim 16 wherein the inhibit means further comprise a second logic array, having the inhibit signal as an input and having the data pulses as another input to provide a phase-shift signal to the phase-shifting means in the absence of an inhibit signal.

Claim 28

The synchronizer of claim 19 wherein the inhibit means further comprise a second logic array, having the inhibit signal as an input and having the data pulses as another input to provide a phase-shift signal to the phase-shifting means in the absence of an inhibit signal.

Claim 29

The synchronizer of claim 23 wherein the inhibit means further comprise a second logic array, having the inhibit signal as an input and having the data pulses as another input to provide a phase-shift signal to the phase-shifting means in the absence of an inhibit signal.

Claim 32

The method of claim 27 further comprising the steps of: f. decoding the counting of the reference pulses to provide an inhibit signal when a predetermined count is reached; and g. inhibiting any phase shift of the clock pulses and any shift in the time of occurrence of the output sampling signal, in the presence of an inhibit signal.

Claim 33

The methof of claim 27 wherein the step of reproducing the clock pulse waveform further comprises: a. i. forming a first single pulse, having a time period twice that of a single pulse of the input pulse train; ii. forming a second single pulse identical to the first single pulse but phase shifted therefrom by one-half of 1 clock cycle in one direction; and iii. conditioning the clock pulses with the first and second single pulses to provide duplicated clock pulses phase shifted in the one direction by one-half of 1 clock cycle.