Data storage and access apparatus

Claim 2

A data storage and access system for storing an N element data field and for providing access to an M element subset of said data field, where M is less than N and where M is greater than or equal to 2, comprising: a shift register element having N stages, a network input line and a network output line and including means for shifting data from stage-to-stage therein in response to a first clock signal, wherein M of the stages of said shift register element are S/A SRA shift registers which are interconnected to provide a closed data loop, and include means for shifting data from register-to-register fully around said closed S/A SRA shift register loop in response to a second clock signal, to periods between shifts in response to said first clock signal, said data shifting means being selectively operative when said subset of said data field is stored in said S/A SRA shift registers, and a system output line coupled to one of said S/A SRA shift registers in said loop whereby said subset of said data field is serially provided in response to said second clock signal.

Claim 3

A system according to claim 1 wherein said network input line is coupled to a source means for serially providing said data field in step with said first clock signal.

Claim 4

A system according to claim 2 wherein said shift registers are digital shift registers.

Claim 5

A system according to claim 2 wherein said shift registers are analog shift registers.

Claim 6

A system according to claim 2 wherein said data field is representative of sampled characteristics of multidimensional data.

Claim 7

A system according to claim 1 wherein said S/A SRA shift registers are adapted for selective interconnection to provide said closed data loop, and wherein said system includes means for selectively interconnecting ones of said S/A SRA shift registers to provide said closed data loop.

Claim 8

A data processor including two or more systems as claimed in claim 1 wherein each network input line is coupled to an associated source means for serially providing a data field in step with said first clock signal.

Claim 9

A data processor according to claim 7 wherein said source means provides said data fields in parallel to the respective ones of said network input lines.

Claim 10

A data processor according to claim 8 wherein each parallelly provided portion of said data fields is a digitally coded word representative of a multidimensional data field.

Claim 11

A data processor according to claim 8 wherein each parallelly provided portion of said data field includes a plurality of analog values representative of parameter values at discrete points in the data space.

Claim 12

A data processor according to claim 7 wherein said S/A SRA shift registers are adapted for selective interconnection to provide said closed data loop, and wherein said data processor includes means for selectively interconnecting ones of said S/A SRA shift registers to provide said closed data loop.

Claim 13

A shift register data storage system for storing an mxnxp bit data field, where m is an integer greater than one and n and p are integers greater than or equal to one, and for providing access to an rxsxt bit subset of said stored data field, where r, s, and t are integers associated with and less than or equal to m, n, and p, respectively, and where at least one of the integers r, s, and t is greater than one, comprising: A. nxp m bit shift register networks, each of said networks including a first network input line and a network output line, said shift register networks being connected in series and wherein at least one of said networks is a composite shift register and includes: a second network input line, an m-r stage SSRA shift register having an SSRA input line coupled to said first network input line for serially receiving digital data, and having an SSRA output line for serially transmitting digital data, said SSRA shift register including means responsive to an applied first succession of clock pulses to transfer data applied at said SSRA input line from stage-to-stage toward said SSRA output line at the rate of said first succession of clock pulses. an r stage S/A SRA shift register having an S/A SRA input line for serially receiving digital data, and having an S/A SRA output line for serially transmitting digital data, said S/A SRA output line being coupled to said network output line, said S/A SRA shift register including means responsive to said first succession of clock pulses to transfer data applied at said S/A SRA input line from stage-to-stage toward said S/A SRA output line at the rate of said first succession of clock pulses, and means responsive to said second succession of clock pulses to transfer data applied at said S/A SRA input line from stage-to-stage toward said S/A SRA output line at the rate of said second succession of clock pulses, means for selectively applying said first succession of clock pulses to said SSRA shift register and said S/A SRA, means for selectively applying an integral multiple of rxsxt pulses of said second succession of clock pulses to said S/A SRA between two pulses of said first succession of clock pulses, shift controller means responsive to each pulse in said first succession to couple a data bit from said SSRA output line to said S/A SRA input line, and responsive to each pulse in said second succession to couple a data bit from said second network input line to said S/A SRA input line, B. means for interconnecting said first input lines, said second network lines, and said network output lines whereby an rxsxt bit subset of said data field is serially provided on a system output line in step with said second succession of clock pulses.

Claim 14

A shift register data storage system for storing an mxnxp bit data field, where m is an integer greater than one and n and p are integers greater than or equal to one, and for providing access to an rxsxt bit subset of said stored data field, where r, s, and t are integers associated with and less than or equal to m, n, and p, respectively, and where at least one of the integers r, s, and t is greater than one, comprising: A. nxp m bit shift register networks, each of said networks including a first network input line and a network output line, said shift register networks being connected in series and wherein at least one of said networks is a composite shift register and includes: a second network input line, an m-r stage SSRA shift register having an SSRA input line coupled to said first network input line for serially receiving digital data, and having an SSRA output line for serially transmitting digital data, said SSRA shift register including means responsive to an applied first succession of clock pulses to transfer data applied at said SSRA input line from stage-to-stage toward said SSRA output line at the rate of said first succession of clock pulses. an r stage S/A SRA shift register having an S/A SRA input line for serially receiving digital data, and having an S/A SRA output line for serially transmitting digital data, said S/A SRA output line being coupled to said network output line, said S/A SRA shift register including means responsive to said first succession of clock pulses to transfer data applied at said S/A SRA input line from stage-to-stage toward said S/A SRA output line at the rate of said first succession of clock pulses, and means responsive to said second succession of clock pulses to transfer data applied at said S/A SRA input line from stage-to-stage toward said S/A SRA output line at the rate of said second succession of clock pulses, means for selectively applying said first succession of clock pulses to said SSRA shift register and said S/A SRA, means for selectively applying an integral multiple of rxsxt pulses of said second succession of clock pulses to said S/A SRA between two pulses of said first succession of clock pulses, shift controller means responsive to each pulse in said first succession to couple a data bit from said SSRA output line to said S/A SRA input line, and responsive to each pulse in said second succession to couple a data bit from said second network input line to said S/A SRA input line, B. means for interconnecting said first input lines, said second network lines, and said network output lines whereby an rxsxt bit subset of said data field is serially provided on a system output line in step with said second succession of clock pulses.

Claim 15

A system according to claim 12 wherein at least one of said composite shift registers provides a closed loop for data transfer through two or more stages of said S/A SRA shift registers in response to said second succession of clock pulses, wherein the second network input line of at least one of said composite shift registers is coupled to one of said network output lines, and the network output line of said one composite shift register is coupled to one of said second network input lines.

Claim 16

A system according to claim 13 wherein said shift register networks are coupled in series, and wherein the first network input line of the first of said shift register networks is coupled to a source means for serially providing said data field in step with said first succession of clock pulses.

Claim 17

A system according to claim 14 wherein said shift registers are digital shift registers.

Claim 18

A system according to claim 14 wherein said shift registers are analog shift registers.

Claim 19

A system according to claim 14 wherein said data field is representative of sampled characteristics of multidimensional data.

Claim 20

A system according to claim 13 wherein said S/A SRA shift registers are adapted for selective interconnection to provide said closed data loop, and wherein said system includes means for selectively interconnecting ones of said S/A SRA shift registers to provide said closed data loop.

Claim 21

A data processor including two or more systems as claimed in claim 13 wherein each network input line is coupled to an associated source means for serially providing a data field in step with said first clock signal.

Claim 22

A data processor according to claim 19 wherein said source means provides said data fields in parallel to the respective ones of said network input lines.

Claim 23

A data processor according to claim 20 wherein each parallelly provided portion of said data fields is a digitally coded word representative of a multidimensional data field.

Claim 24

A data processor according to claim 20 wherein each parallelly provided portion of said data field includes a plurality of analog values representative of parameter values at discrete points in the data space.

Claim 25

A data processor according to claim 19 wherein said S/A SRA shift registers are adapted for selective interconnection to provide said closed data loop, and wherein said data processor includes means for selectively interconnecting ones of said S/A SRA shift registers to provide said closed data loop.