Multiplexed and interlaced charge-coupled serial-parallel-serial memory device

Claim 2

A charge-coupled memory device comprising a first serial-parallel-serial loop including a first serial input section, a first parallel section and a first serial output section, a second serial-parallel-serial loop including a second serial input section, a second parallel section and a second serial output section, input means for receiving a serial data bit stream including a first record comprising a first serial train of bits and a second record comprising a second serial train of bits, first clocking means for transmitting the alternate odd bits of said first record to said first serial input section, second clocking means for transmitting the alternate even bits of said first record to said second serial input section, third clocking means for transmitting the alternate even bits of said second record to said first serial input section, fourth clocking means for transmitting the alternate odd bits of said second record to said second serial input section, means for converting said bits into charge packets, and means for transferring the respective charge packets through said first and second serial input sections, then through said first and second parallel sections and then through said first and second serial output sections.

Claim 3

A charge-coupled memory device as recited in claim 1 and comprising output means, means transmitting said bits from said serial output sections to said output means, said output means including fifth clocking means for transmitting said bits of said first record in the same sequential order as said first serial train and for transmitting said bits of said second record in the same sequential order as said second serial train.

Claim 4

A charge-coupled memory device as recited in claim 1 wherein said first and second clocking means include means for interlacing in said first parallel section said odd bits of the first record with said even bits of the second record, and said third and fourth clocking means include means for interlacing in said second parallel section said even bits of the first record with said odd bits of the second record.

Claim 5

A charge-coupled memory device as recited in claim 1 and comprising output means, means transmitting said bits from said serial output sections to said output means, said output means including fifth clocking means for transmitting said bits of said first record in the same sequential order as said first serial train and for transmitting said bits of said second record in the same sequential order as said second serial train, said first and second clocking means including means for interlacing in said first parallel section said odd bits of the first record with said even bits of the second record, and said third and fourth clocking means including means for interlacing in said second parallel section said even bits of the first record with said odd bits of the second record.

Claim 6

A charge-coupled memory device comprising a plurality of serial-parallel-serial loops each including a serial input section, a parallel section and a serial output section, input means for receiving a serial data bit stream including a plurality of records each comprising a serial train of bits having an original predetermined sequential order, means for transmitting a first set of bits of one record to one of said serial input sections, means for transmitting a second set of bits of said one record to another of said serial input sections, means for transmitting a first set of bits of another record to said another serial input section, means for transmitting a second set of bits of said another record to said one serial input section, means for converting said bits into charge packets, and means for transferring the respective charge packets through said serial input sections, then through said parallel sections and then through said serial output sections.

Claim 7

A charge-coupled memory device comprising a plurality of serial-parallel-serial loops each including a serial input section, a parallel section and a serial output section, input means for receiving a serial data bit stream including a plurality of records each comprising a serial train of bits having an original predetermined sequential order, means for transmitting a first set of bits of one record to one of said serial input sections, means for transmitting a second set of bits of said one record to another of said serial input sections, means for transmitting a first set of bits of another record to said another serial input section, means for transmitting a second set of bits of said another record to said one serial input section, means for converting said bits into charge packets, and means for transferring the respective charge packets through said serial input sections, then through said parallel sections and then through said serial output sections.

Claim 8

A charge-coupled memory device as recited in claim 5 and comprising output means, means transmitting said bits from said serial output sections to said output means, said output means including means for transmitting said bits of said one record in the same sequential order as the original predetermined order thereof and for transmitting said bits of said another record in the same sequential order as the original predetermined order thereof.

Claim 9

A charge-coupled memory device as recited in claim 5 wherein said transmitting means include means for interlacing in one of said parallel sections said first set of bits of said one record with said second set of bits of said another record, and said transmitting means include means for interlacing in said another parallel section said second set of bits of said one record with said first set of bits of said another record.

Claim 10

A charge-coupled memory device as recited in claim 5 and comprising output means, means transmitting said bits from said serial output sections to said output means, said output means including means for transmitting said bits of said first record in the same sequential order as the original predetermined order thereof and for transmitting said bits of said another record in the same sequential order as the original predetermined order thereof, said transmitting means including means for interlacing in one of said parallel sections said first set of bits of said one record with said second set of bits of said another record, and said transmitting means including means for interlacing in said another parallel section said second set of bits of said one record with said first set of bits of said another record.

Claim 11

A charge-coupled memory device comprising a first serial-parallel-serial loop, a second serial-parallel-serial loop, input means for receiving a serial data bit stream including one record comprising one serial train of bits and a different record comprising a different serial train of bits, clocking means for transmitting the alternate odd bits of said one record to said first loop and for transmitting the alternate even bits of said one record to said second loop, clocking means for transmitting the alternate even bits of said different record to said first loop and for transmitting the alternate odd bits of said different record to said second loop, said clocking means including means for interlacing in said first loop said odd bits of said one record with said even bits of said different record, said clocking means including means for interlacing in said second loop said even bits of said one record with said odd bits of said different record, output means, means transmitting said bits from said loops to said output means, said output means including clocking means for transmitting said bits of said one record in the same sequential order as said one serial train and for transmitting said bits of said different record in the same sequential order as said different serial train.

Claim 12

A charge-coupled memory device comprising a first serial-parallel-serial loop, a second serial-parallel-serial loop, input means for receiving a serial data bit stream including one record comprising one serial train of bits and a different record comprising a different serial train of bits, clocking means for transmitting the alternate odd bits of said one record to said first loop and for transmitting the alternate even bits of said one record to said second loop, clocking means for transmitting the alternate even bits of said different record to said first loop and for transmitting the alternate odd bits of said different record to said second loop, said clocking means including means for interlacing in said first loop said odd bits of said one record with said even bits of said different record, said clocking means including means for interlacing in said second loop said even bits of said one record with said odd bits of said different record, output means, means transmitting said bits from said loops to said output means, said output means including clocking means for transmitting said bits of said one record in the same sequential order as said one serial train and for transmitting said bits of said different record in the same sequential order as said different serial train.