Machine for multiple instruction execution

Claim 9

In apparatus for computing instructions compiled into groups of n, where n is an integer >1, instructions, with no more than a fixed number of data and branch instruction fetches and a fixed number of store operations being permitted in a group, and any branch instruction being the last instruction in the group, the combination comprising: an instruction cache in which said groups of n instructions and said branch instructions are stored; a data cache in which data to be used in the execution of said instructions is stored; a group of general purpose registers in which data read from said data cache is stored; an n stage register in which a group of n instructions at a time read from said instruction cache is stored; an instruction address generator for generating branch instruction fetches in response to a branch instruction being stored in said n stage register; at least one data address generator for generating data fetches from said general purpose registers in response to a data fetch instruction being stored in said n stage register; a switching and logic unit responsive to said n instructions in said n stage register for routing any instruction or data fetches to said instruction and data address generators, respectively, with said address generators being operative with said instruction cache, data cache and general purpose registers; and n execution logic means for responding to each of said n instructions and said switching and logic units and address generators for concurrently executing each of said n instructions, and performing said store operation in said data cache when called for.

Claim 10

In apparatus for computing instructions compiled into groups of n, where n is an integer >1, instructions, with no more than a fixed number of data and branch instruction fetches and a fixed number of store operations being permitted in a group, and any branch instruction being the last instruction in the group, the combination comprising: an instruction cache in which said groups of n instructions and said branch instructions are stored; a data cache in which data to be used in the execution of said instructions is stored; a group of general purpose registers in which data read from said data cache is stored; an n stage register in which a group of n instructions at a time read from said instruction cache is stored; an instruction address generator for generating branch instruction fetches in response to a branch instruction being stored in said n stage register; at least one data address generator for generating data fetches from said general purpose registers in response to a data fetch instruction being stored in said n stage register; a switching and logic unit responsive to said n instructions in said n stage register for routing any instruction or data fetches to said instruction and data address generators, respectively, with said address generators being operative with said instruction cache, data cache and general purpose registers; and n execution logic means for responding to each of said n instructions and said switching and logic units and address generators for concurrently executing each of said n instructions, and performing said store operation in said data cache when called for.

Claim 11

In apparatus for computing instructions of a given type compiled into groups of n, where n is an integer ≧4, instructions, with no more than one instruction being other than said given type and said one instruction being at a fixed position from one group to the next, with two data fetches and one branch instruction fetch and one store operation being permitted in a group, with any branch instruction fetch being the last instruction in the group, the combination comprising: an instruction cache wherein said groups of n instructions including branch instructions are stored; a data cache containing data necessary to perform said instructions; an n stage register in which a group of n instructions at a time is stored from said instruction cache, with any instruction other than said given type being stored in a predetermined one of said n stages; a first gating means responsive to the instruction stored in said predetermined one of said n stages for determining if the instruction is of said given type, and if so permitting same to be processed by said apparatus; a second gating means responsive to each of said n instructions for determining which instructions, if any, contains a branch instruction fetch; a third gating means responsive to each of said n instructions for determining which instruction, if any, contains a first data fetch; a fourth gating means responsive to each of said n instructions for determining which instruction, if any, contains a second data fetch; a group of general purpose registers in which addresses and data needed for executing said instructions are stored; an instruction address generation means operative with said general purpose registers and responsive to said second gating means for initiating a branch instruction fetch from said instruction cache; a first data address generation means operative with said data cache and general purpose registers and responsive to said third gating means for fetching addresses and data; a second data address generation means operative with said data cache and general purpose registers and responsive to said fourth gating means for fetching addresses and data; and n execution logic means, each operative with one of said n stages of said n stage register and said first and second data and address generators for concurrently executing the called for valid instructions of said given type including called for data fetches and store operations, if any, with the address and data called for by said store operation being provided to said data cache.

Claim 12

In apparatus for computing instructions of a given type compiled into groups of n, where n is an integer ≧4, instructions, with no more than one instruction being other than said given type and said one instruction being at a fixed position from one group to the next, with two data fetches and one branch instruction fetch and one store operation being permitted in a group, with any branch instruction fetch being the last instruction in the group, the combination comprising: an instruction cache wherein said groups of n instructions including branch instructions are stored; a data cache containing data necessary to perform said instructions; an n stage register in which a group of n instructions at a time is stored from said instruction cache, with any instruction other than said given type being stored in a predetermined one of said n stages; a first gating means responsive to the instruction stored in said predetermined one of said n stages for determining if the instruction is of said given type, and if so permitting same to be processed by said apparatus; a second gating means responsive to each of said n instructions for determining which instructions, if any, contains a branch instruction fetch; a third gating means responsive to each of said n instructions for determining which instruction, if any, contains a first data fetch; a fourth gating means responsive to each of said n instructions for determining which instruction, if any, contains a second data fetch; a group of general purpose registers in which addresses and data needed for executing said instructions are stored; an instruction address generation means operative with said general purpose registers and responsive to said second gating means for initiating a branch instruction fetch from said instruction cache; a first data address generation means operative with said data cache and general purpose registers and responsive to said third gating means for fetching addresses and data; a second data address generation means operative with said data cache and general purpose registers and responsive to said fourth gating means for fetching addresses and data; and n execution logic means, each operative with one of said n stages of said n stage register and said first and second data and address generators for concurrently executing the called for valid instructions of said given type including called for data fetches and store operations, if any, with the address and data called for by said store operation being provided to said data cache.