Patent US4295176A successfully refreshed from Google Patents.
US4295176A
Expired / Lapsed
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Semiconductor integrated circuit protection arrangement
Assignee: AT&T Inc
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Filing: 1979-09-04
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Granted: 1981-10-13
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Expires: 1999-09-04
Abstract
Abstract An array of semiconductor circuits integrated in a single semiconductor body substrate, each circuit having a separate input terminal, is protected from overvoltages in the inputs by means of a separate diode for each such circuit connected between its protected input node and a reference terminal (V DD ) in common with all the other circuits. In addition, the high current path of a single auxiliary transistor is arranged to provide, in the presence of overvoltages, a low resistance path between the reference terminal (V DD ) and the wide area substrate contact V SS in order to protect the input nodes in case of overvoltages when reference terminal (V DD ) is disconnected ("floating").
Inventors
- 👤 Norman C. Wittwer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:03
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08122; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
159 words
Semiconductor apparatus comprising an overvoltage protection arrangement for a multiplicity of MOSFET circuits (16, 26, . . . 96) integrated in a single semiconductor body at a first major surface thereof, characterized by means for connecting a node (16.5, 26.5, . . . 96.5) of each of said circuits through the high current path of an auxiliary transistor, (T 1 ), integrated in said semiconductor body to an electrode in wide area contact with a second opposed major surface of said body, and with a common reference voltage metalization line (101) connected (18, 28, . . . 98) to each said circuit for providing the reference voltage thereto, said means including a separate unidirectional current inhibiting device (17, 27, . . . 97) connected between each said node (16.5, 26.5, . . . 96.5) and the common line (101), the common line being connected through bidirectional current conducting means (102) to the high current path of the auxiliary transistor.
Claim 2
Dependent Claim
159 words
Semiconductor apparatus comprising an overvoltage protection arrangement for a multiplicity of MOSFET circuits (16, 26, . . . 96) integrated in a single semiconductor body at a first major surface thereof, characterized by means for connecting a node (16.5, 26.5, . . . 96.5) of each of said circuits through the high current path of an auxiliary transistor, (T 1 ), integrated in said semiconductor body to an electrode in wide area contact with a second opposed major surface of said body, and with a common reference voltage metalization line (101) connected (18, 28, . . . 98) to each said circuit for providing the reference voltage thereto, said means including a separate unidirectional current inhibiting device (17, 27, . . . 97) connected between each said node (16.5, 26.5, . . . 96.5) and the common line (101), the common line being connected through bidirectional current conducting means (102) to the high current path of the auxiliary transistor.
Claim 3
Dependent Claim
106 words
Semiconductor apparatus comprising: (a) an array of semiconductor logic circuits integrated in a single semiconductor body at a first major surface thereof, each said logic circuit in the array having a separate input node and each said logic circuit separately connected to a common metallization line for providing a reference voltage to each said circuit; (b) a separate first unidirectional current inhibiting device connected between each said input node and the common metallization line; (c) an auxiliary transistor (T 1 ) whose high current path is connected between said common line and a wide area contact electrode on a second opposed major surface of the body.
Claim 4
Dependent Claim
106 words
Semiconductor apparatus comprising: (a) an array of semiconductor logic circuits integrated in a single semiconductor body at a first major surface thereof, each said logic circuit in the array having a separate input node and each said logic circuit separately connected to a common metallization line for providing a reference voltage to each said circuit; (b) a separate first unidirectional current inhibiting device connected between each said input node and the common metallization line; (c) an auxiliary transistor (T 1 ) whose high current path is connected between said common line and a wide area contact electrode on a second opposed major surface of the body.
Claim 5
Dependent Claim
50 words
Apparatus according to claim 2 in which each said auxiliary transistor is a separate MOSFET, in which each said input node is the gate electrode of a separate input MOSFET, and in which each said input node is separately connected through a separate resistor to a separate input signal terminal.
Claim 6
Dependent Claim
53 words
Apparatus according to claim 3 which further includes a second separate unidirectional current inhibiting device connected between said input signal terminal and the bulk of said semiconductor body, each said second inhibiting device directed with respect to said input node in the opposite sense from that of the corresponding said first inhibiting device.
Claim 7
Dependent Claim
45 words
Apparatus according to claim 3 in which the conductance of each said first current inhibiting device in its forward direction is at least an order of magnitude greater than the conductance of the resistor connected to the same input node as said current inhibiting device.
Claim 8
Dependent Claim
53 words
Apparatus according to claim 2 which further includes a second separate unidirectional current inhibiting device connected between said input signal terminal and the bulk of said semiconductor body, each said second inhibiting device directed with respect to said input node in the opposite sense from that of the corresponding said first inhibiting device.
Claim 9
Dependent Claim
55 words
Apparatus according to claim 6 in which each said resistor and each said second unidirectional current inhibiting device connected to the same input signal terminal is provided by an impurity region at said first major surface of opposite conductivity type from that of the bulk of the body in a neighborhood of the logic circuits.
Claim 10
Dependent Claim
46 words
Apparatus in accordance with claim 7 in which the conductance of each said first current inhibiting device in its forward direction is at least an order of magnitude greater than the conductance of the resistor connected to the same input node as said current inhibiting device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |