Patent US4292730A successfully refreshed from Google Patents.
US4292730A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization
Assignee: Intersil Corp
•
Filing: 1980-03-12
•
Granted: 1981-10-06
•
Expires: 2000-03-12
Abstract
Abstract A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base. The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.
Inventors
- 👤 Kenneth A. Ports
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:16
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W20/00; H10W20/01; H10W20/021; H10W20/40; H10W10/011; H10W10/014; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/02; Y10S148/085; Y10S148/136; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
145 words
In a method of fabricating an integrated circuit having mesa devices including forming an epitaxial layer on a substrate, forming a top support on said epitaxial layer and removing said substrate, the improvement comprising: applying a backside metallic layer to the bottom of said epitaxial layer; forming a bottom support on said backside metallic layer; removing said top support; etching said epitaxial layer to form a plurality of discrete mesa; etching said backside metallic layer to form a discrete backside contact for each mesa; forming a first top insulative layer; applying first interconnect layer and delineating to form interconnects on said first insulating layer between said mesa and contacts to said mesa; forming a second top insulative layer; and applying a second interconnect layer and delineating to form interconnects on said second insulating layer between said mesa and contacts to surface regions of said mesa.
Claim 2
Dependent Claim
145 words
In a method of fabricating an integrated circuit having mesa devices including forming an epitaxial layer on a substrate, forming a top support on said epitaxial layer and removing said substrate, the improvement comprising: applying a backside metallic layer to the bottom of said epitaxial layer; forming a bottom support on said backside metallic layer; removing said top support; etching said epitaxial layer to form a plurality of discrete mesa; etching said backside metallic layer to form a discrete backside contact for each mesa; forming a first top insulative layer; applying first interconnect layer and delineating to form interconnects on said first insulating layer between said mesa and contacts to said mesa; forming a second top insulative layer; and applying a second interconnect layer and delineating to form interconnects on said second insulating layer between said mesa and contacts to surface regions of said mesa.
Claim 3
Dependent Claim
28 words
The method according to claim 1 wherein said first interconnect layer is a polycrystalline semiconductor and including doping said polycrystalline layer and delineating to form interconnects and resistors.
Claim 4
Dependent Claim
58 words
The method according to claim 1 including diffusing impurities of a first conductivity type into the epitaxial mesa of a second conductivity type opposite said first conductivity type to form a first PN junction and diffusing impurities of said second conductivity type into the region formed by diffusing said first conductivity impurities to form a second PN junction.
Claim 5
Dependent Claim
34 words
The method according to claim 1 wherein said bottom support is formed by applying a backside insulative layer to said backside metallic layer and applying a polycrystalline semiconductor layer to said backside insulative layer.
Claim 6
Dependent Claim
15 words
The method according to claim 1 wherein said substrate is totally removed by electro-chemical etching.
References Cited (Backward Citations)
US3432919A
Cited
US3480841A
Cited
US3506502A
Cited
US3519901A
Cited
US3659162A
Cited
US4189342A
Cited
US4035830A
Cited
US4146905A
Cited
US4017341A
Cited
US4131909A
Cited
US4131985A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-05 | 1985-04-06 | 1985-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-05 | 1989-04-06 | 1989-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-05 | 1993-04-06 | 1993-10-06 | $7700.00 | Window Closed / Lapsed |