US4292728A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing semiconductor integrated circuits utilizing special contact formation
Assignee: Toshiba Corp
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Filing: 1979-06-13
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Granted: 1981-10-06
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Expires: 1999-06-13
Abstract
Abstract A method for manufacturing semiconductor integrated circuits such as metal oxide semiconductor field effect transistors having source and drain regions to which contact holes are made such that not only the contact parts of the source and the drain regions, but also both surface parts of a field oxide layer which are adjacent to the outer edges of source and drain regions, are exposed and contacted.
Inventors
- 👤 Norio Endo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P76/00; H10P76/40; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10W20/00; H10W20/01; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/02; Y10S148/106
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
181 words
A method for manufacturing semiconductor integrated circuits, comprising the steps of: forming a field oxide layer on a semiconductor substrate; partially removing the field oxide layer to expose a predetermined part of said semiconductor substrate; forming in said exposed part of the semiconductor substrate insulated gate field effect transistors having insulated gates and source and drain edge regions adjacent to said field oxide layer; forming a first insulating layer which has a different etching rate from said field oxide layer on the overall surface of said field oxide layer and said transistors; forming on the first insulating layer a second insulating layer which has a different etching rate from said first insulating layer; removing portions of said second insulating layer which are situated above the edge part of said field oxide layer and parts of said source and drain regions distant from the gate by using an etching material which substantially only etches said second insulating layer, and etching the first insulating layer by using the second insulating layer as a mask, thus forming contact holes to the field effect transistors.
Claim 2
Independent Claim
181 words
A method for manufacturing semiconductor integrated circuits, comprising the steps of: forming a field oxide layer on a semiconductor substrate; partially removing the field oxide layer to expose a predetermined part of said semiconductor substrate; forming in said exposed part of the semiconductor substrate insulated gate field effect transistors having insulated gates and source and drain edge regions adjacent to said field oxide layer; forming a first insulating layer which has a different etching rate from said field oxide layer on the overall surface of said field oxide layer and said transistors; forming on the first insulating layer a second insulating layer which has a different etching rate from said first insulating layer; removing portions of said second insulating layer which are situated above the edge part of said field oxide layer and parts of said source and drain regions distant from the gate by using an etching material which substantially only etches said second insulating layer, and etching the first insulating layer by using the second insulating layer as a mask, thus forming contact holes to the field effect transistors.
Claim 3
Dependent Claim
42 words
A method according to claim 1, further comprising: covering the device surface with a thin oxide layer prior to the forming of said first insulating layer; and said etching of said first insulating layer comprising plasma etching of said first insulating layer.
Claim 4
Dependent Claim
22 words
A method for manufacturing semiconductor integrated circuits according to claim 1 or claim 2, wherein said insulated gates are formed of polysilicon.
Claim 5
Dependent Claim
28 words
A method for manufacturing semiconductor integrated circuits according to claim 1, wherein said first and second insulating layers are formed of silicon nitride and thermal silicon oxide, respectively.
Claim 6
Dependent Claim
33 words
A method for manufacturing semiconductor integrated circuits according to claim 3 wherein said step of forming said insulated gate further comrises: forming a polysilicon metallization on a part of said field oxide layer.
Claim 7
Dependent Claim
30 words
A method for manufacturing semiconductor integrated circuits according to claim 5, further comrising: forming a contact hole to the polysilicon metallization, said contact hole extending out beyond the polysilicon metallization.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-05 | 1985-04-06 | 1985-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-05 | 1989-04-06 | 1989-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-05 | 1993-04-06 | 1993-10-06 | $7700.00 | Window Closed / Lapsed |