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US4282646A
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Method of making a transistor array
Assignee: International Business Machines Corp
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Filing: 1979-08-20
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Granted: 1981-08-11
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Expires: 1999-08-20
Abstract
Abstract A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.
Inventors
- 👤 Andres G. Fortino
- 👤 Henry J. Geipel, Jr.
- 👤 Lawrence G. Heller
- 👤 Ronald Silverman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:35
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/387; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1404; H10P32/1406; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
122 words
A method of making an array of transistors which includes: forming a plurality of gate electrodes insulated from a semiconductor substrate having a given type conductivity, introducing a first impurity having a conductivity opposite to that of said given type conductivity into regions of said substrate defined by an edge of each of said gate electrodes, introducing a second impurity into selected ones of said regions along the edge of their associated gate electrodes, said second impurity having an opposite conductivity to and a significantly higher diffusivity than that of said first impurity, and heating said substrate to drive said second impurity through said substrate under the associated gate electrodes to decrease the conductivity of said substrate under said associated gate electrodes.
Claim 2
Independent Claim
122 words
A method of making an array of transistors which includes: forming a plurality of gate electrodes insulated from a semiconductor substrate having a given type conductivity, introducing a first impurity having a conductivity opposite to that of said given type conductivity into regions of said substrate defined by an edge of each of said gate electrodes, introducing a second impurity into selected ones of said regions along the edge of their associated gate electrodes, said second impurity having an opposite conductivity to and a significantly higher diffusivity than that of said first impurity, and heating said substrate to drive said second impurity through said substrate under the associated gate electrodes to decrease the conductivity of said substrate under said associated gate electrodes.
Claim 3
Dependent Claim
43 words
A method of making an array of transistors as set forth in claim 1 wherein said substrate has a given impurity concentration and wherein the concentration of said higher diffusivity impurity under said associated electrode gates is higher than said given impurity concentration.
Claim 4
Dependent Claim
74 words
A method of making an array of transistors as set forth in claim 1 wherein the first impurity is introduced into first regions of said substrate adjacent to a first edge of each of said gate electrodes and into second regions of said substrate adjacent to a second edge of each of said gate electrodes disposed on the opposite side of said gate electrode from said first edge for forming source and drain regions.
Claim 5
Dependent Claim
30 words
A method of making an array of transistors as set forth in claim 3 wherein said second impurity is introduced into selected ones of said first regions of said substrate.
Claim 6
Dependent Claim
36 words
A method of making an array of transistors as set forth in claim 4 wherein said first impurity is arsenic, said second impurity is boron and the given conductivity of said semiconductor substrate is P type.
Claim 7
Independent Claim
163 words
A method of making a read only memory having an array of field effect transistors including the step of: forming a plurality of gate electrodes insulated from channel region in a semiconductor substrate having a given conductivity, introducing a first impurity of a conductivity opposite to that of said given conductivity into a region of said substrate defined by an edge of each of said gate electrodes, introducing a second impurity of said given conductivity into selected ones of said regions along the edge of their associated gate electrodes, said second impurity having a higher diffusivity than that of said first impurity, heating said substrate to drive said second impurity through said substrate so as to form a halo-like region with respect to said first impurity for altering said given conductivity of said substrate adjacent to said gate electrodes in said channel regions, and connecting sensing means to each of said regions for determining the location of said halo-like regions in said substrate.
Claim 8
Independent Claim
163 words
A method of making a read only memory having an array of field effect transistors including the step of: forming a plurality of gate electrodes insulated from channel region in a semiconductor substrate having a given conductivity, introducing a first impurity of a conductivity opposite to that of said given conductivity into a region of said substrate defined by an edge of each of said gate electrodes, introducing a second impurity of said given conductivity into selected ones of said regions along the edge of their associated gate electrodes, said second impurity having a higher diffusivity than that of said first impurity, heating said substrate to drive said second impurity through said substrate so as to form a halo-like region with respect to said first impurity for altering said given conductivity of said substrate adjacent to said gate electrodes in said channel regions, and connecting sensing means to each of said regions for determining the location of said halo-like regions in said substrate.
Claim 9
Dependent Claim
40 words
A method of making a read only memory as set forth in claim 6 wherein said impurities are introduced by ion implantation to form in said halo-like region a concentration of said second impurity higher than that in said substrate.
Claim 10
Dependent Claim
43 words
A method of making a read only memory as set forth in claim 7 wherein said first impurity is arsenic, said second impurity is boron and said semiconductor substrate has a P type conductivity and wherein said sensing means are current sensing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-10 | 1985-02-09 | 1985-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-10 | 1989-02-09 | 1989-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-10 | 1993-02-09 | 1993-08-11 | $7700.00 | Window Closed / Lapsed |