US4131983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustment of avalanche voltage in DIFMOS memory devices by control of impurity doping
Assignee: Texas Instruments Inc
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Filing: 1977-01-10
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Granted: 1979-01-02
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Expires: 1997-01-10
Abstract
Abstract A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.
Inventors
- 👤 Walter T. Matzen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:15
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
207 words
A method for the fabrication of a semiconductor memory device having a floating gate, a sense transistor, an electron injector and a hole injector, comprising the steps of: a) forming a p- region in an n-type semiconductor substrate; b) then forming at least three p+ regions in said substrate, one of which is contiguous with said p- region, and two others of which form the source and drain at said sense transistor; c) then forming an n+ region in said substrate, also contiguous with said p- region; d) then implanting an n-type region in said substrate which overlaps a portion of said n+ region and a portion of said source or said drain, said implanted region having a dopant concentration between 5 × 10 16 and 2 × 10 17 cm -3 ; e) then forming said floating gate with selected portions spaced narrowly from (1) the channel region between said source and drain, (2) the p+n+ junction formed by said implanted region, and (3) the n+p- junction formed by said p- region and contiguous n+ region; whereby the implanted n+ region together with its overlapped p+ region forms the electron injector junction, said p- region together with its contiguous n+ region forms the hole injector region.
Claim 2
Independent Claim
207 words
A method for the fabrication of a semiconductor memory device having a floating gate, a sense transistor, an electron injector and a hole injector, comprising the steps of: a) forming a p- region in an n-type semiconductor substrate; b) then forming at least three p+ regions in said substrate, one of which is contiguous with said p- region, and two others of which form the source and drain at said sense transistor; c) then forming an n+ region in said substrate, also contiguous with said p- region; d) then implanting an n-type region in said substrate which overlaps a portion of said n+ region and a portion of said source or said drain, said implanted region having a dopant concentration between 5 × 10 16 and 2 × 10 17 cm -3 ; e) then forming said floating gate with selected portions spaced narrowly from (1) the channel region between said source and drain, (2) the p+n+ junction formed by said implanted region, and (3) the n+p- junction formed by said p- region and contiguous n+ region; whereby the implanted n+ region together with its overlapped p+ region forms the electron injector junction, said p- region together with its contiguous n+ region forms the hole injector region.
Claim 3
Dependent Claim
29 words
A method as in claim 1 wherein said implantation step comprises a dose of 1.0 × 10 13 cm -2 phosphorus atoms, accelerated to an energy of 100 Kev.
Claim 4
Dependent Claim
21 words
A method as in claim 1 wherein the distance between said regions overlapped by the implantation step is about 0.5 mil.
References Cited (Backward Citations)
US3881180A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-01 | 1982-07-03 | 1983-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-01 | 1986-07-03 | 1987-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-01 | 1990-07-03 | 1991-01-02 | $7700.00 | Window Closed / Lapsed |