Patent US4256515A successfully refreshed from Google Patents.
US4256515A
Expired / Lapsed
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Method for making integrated circuit with C-MOS logic, bipolar driver and polysilicon resistors
Assignee: Allegro Microsystems LLC
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Filing: 1979-10-26
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Granted: 1981-03-17
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Expires: 1999-10-26
Abstract
Abstract An integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer. High value polysilicon resistors are formed over an outer protective silicon dioxide layer of the silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors. The process for making the integrated circuit includes forming a sheet of polysilicon over the entire wafer surface, performing the ion implantation and etching away all but the desired resistor portions of the polysilicon. It also includes heating the wafer to simultaneously anneal the ion implanted polysilicon, form the gate oxide, thicken the oxide over the emitters, and cover the resistor body with a thin protective oxide film.
Inventors
- 👤 Steven W. Miles
- 👤 Paul R. Emerald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:48
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/01; H03K5/02; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D88/00; H10P; H10P32/00; H10P32/30; H10P32/302; H10P95/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
171 words
A method for making an integrated circuit having a complimentary pair of MOS transistors, a PNP transistor, an NPN transistor and a resistor comprising: (a) growing an N-type epitaxial layer over the face of a P-type silicon crystal wafer; (b) electrically isolating a first, second and third pocket from each other in said epitaxial layer; (c) selectively doping said epitaxial layer from the outer surface thereof to form a complimentary pair of MOS transistors in said first pocket, an NPN transistor in said second pocket and a PNP transistor in said third pocket; (d) forming an insulative film over said surface; (e) depositing a polysilicon sheet over said entire surface on said film; (f) doping by ion implantation said polysilicon sheet so that substantially all of said implanted ions remain within said sheet; (g) selectively removing portions of said sheet to form an ion implanted polysilicon resistor body; (h) heating to anneal said ion implanted resistor body; and (i) providing aluminum film electrical connections to said resistor and to said transistors.
Claim 2
Independent Claim
171 words
A method for making an integrated circuit having a complimentary pair of MOS transistors, a PNP transistor, an NPN transistor and a resistor comprising: (a) growing an N-type epitaxial layer over the face of a P-type silicon crystal wafer; (b) electrically isolating a first, second and third pocket from each other in said epitaxial layer; (c) selectively doping said epitaxial layer from the outer surface thereof to form a complimentary pair of MOS transistors in said first pocket, an NPN transistor in said second pocket and a PNP transistor in said third pocket; (d) forming an insulative film over said surface; (e) depositing a polysilicon sheet over said entire surface on said film; (f) doping by ion implantation said polysilicon sheet so that substantially all of said implanted ions remain within said sheet; (g) selectively removing portions of said sheet to form an ion implanted polysilicon resistor body; (h) heating to anneal said ion implanted resistor body; and (i) providing aluminum film electrical connections to said resistor and to said transistors.
Claim 3
Dependent Claim
45 words
The method of claim 1 additionally comprising selectively removing said insulative film from over the gate regions of said MOS transistors and simultaneously with said heating, growing a thin silicon dioxide film over said gate regions and over the body of said polysilicon resistor body.
Claim 4
Dependent Claim
60 words
The method of claim 1 wherein said isolating includes selectively depositing P-type impurities on said face of said wafer prior to said epitaxial growing step, selectively diffusing impurities at the surface of said epitaxial layer and raising the temperature of said wafer to drive said impurities further into said epitaxial layer to form P-type walls extending through said epitaxial layer.
Claim 5
Dependent Claim
53 words
The method of claim 3 wherein said selective doping includes, simultaneously with said selectively depositing, and raising the temperature, also selectively doping the P-type impurities on a portion of said epitaxial surface corresponding to the location of the N-channel transistor of said pair and raising the temperature to form a P-well region there.
Claim 6
Dependent Claim
76 words
The method of claim 3 additionally comprising selectively diffusing P-type impurities at said surface to form a heavily doped shallow region overlapping said isolation wall, said selectively doping to form said transistors including simultaneously with said selectively diffusing, diffusing P-type impurities at said surface to form the base region of said NPN transistor, the emitter and collector regions of said PNP transistor and the source and drain regions of the P-channel transistor of said MOS pair.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-16 | 1984-09-15 | 1985-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-16 | 1988-09-15 | 1989-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-16 | 1992-09-15 | 1993-03-17 | $7700.00 | Window Closed / Lapsed |