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US4240846A
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US
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Method of fabricating up diffused substrate FED logic utilizing a two-step epitaxial deposition
Assignee: Harris Corp
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Filing: 1978-06-27
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Granted: 1980-12-23
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Expires: 1998-06-27
Abstract
Abstract A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurity concentration of the buried region decreases from its junction with the first epitaxial layer to its junction with the second epitaxial layer whose impurity concentration is less than that of the first epitaxial layer. High impurity concentration N type guard ring and P type base ring are diffused simultaneously with the out diffusion of the buried P type region into the second epitaxial layer. The substrate, first epitaxial layer and buried region constitute the emitter, base, and collector of the inverse vertical PNP transistor and the first epitaxial layer, buried region and second epitaxial layer constitute the emitter, base, and collector of the inverse vertical NPN transistor.
Inventors
- 👤 Brent R. Doyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:17
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/652; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
91 words
A method of fabricating a substrate fed logic semiconductor structure having an injector and complementary transistor comprising: epitaxially forming a first N conductivity type layer on a P conductivity type substrate having a lower impurity concentration than said substrate; depositing P conductivity type impurities at the surface of said first layer having an impurity concentration less than said first layer; epitaxially forming a second N conductivity type layer on said first layer having an impurity concentration less than the impurity concentration of said first layer and deposited P conductivity type impurities;
Claim 2
Independent Claim
91 words
A method of fabricating a substrate fed logic semiconductor structure having an injector and complementary transistor comprising: epitaxially forming a first N conductivity type layer on a P conductivity type substrate having a lower impurity concentration than said substrate; depositing P conductivity type impurities at the surface of said first layer having an impurity concentration less than said first layer; epitaxially forming a second N conductivity type layer on said first layer having an impurity concentration less than the impurity concentration of said first layer and deposited P conductivity type impurities;
Claim 3
Dependent Claim
132 words
depositing P conductivity type impurities in the surface of said second layer having a greater impurity concentration than said P conductivity type impurities at the surface of said first layer; and simultaneously diffusing said P conductivity type impurities up from the surface of said first layer into said second layer and P conductivity type impurities down from the surface of said second layer to form a buried P conductivity type region between said two layers and a P conductivity type region extending from the surface of said second layer down to said buried region; said substrate, first layer and buried region forming the emitter, base and collector of the injector transistor, respectively and said first layer, buried region and second layer form the emitter, base and collector of the complementary transistor, respectively.
Claim 4
Dependent Claim
132 words
depositing P conductivity type impurities in the surface of said second layer having a greater impurity concentration than said P conductivity type impurities at the surface of said first layer; and simultaneously diffusing said P conductivity type impurities up from the surface of said first layer into said second layer and P conductivity type impurities down from the surface of said second layer to form a buried P conductivity type region between said two layers and a P conductivity type region extending from the surface of said second layer down to said buried region; said substrate, first layer and buried region forming the emitter, base and collector of the injector transistor, respectively and said first layer, buried region and second layer form the emitter, base and collector of the complementary transistor, respectively.
Claim 5
Dependent Claim
65 words
The method according to claim 1 wherein said first and second epitaxial layers are formed to have an impurity concentration differing by approximately two orders of magnitude and said P conductivity type impurities are deposited at the surface of said first layer to form said buried region having an impurity concentration of the order of magnitude of said second epitaxial layer at the junction therebetween.
Claim 6
Dependent Claim
78 words
The method according to claim 1 wherein said P conductivity type impurities are deposited at the surface of said first layer and upwardly diffused to form said buried region having an impurity concentration equal to the impurity concentration of said second epitaxial layer at the junction therebetween and said buried layer impurity concentration increasing toward the junction of said buried region and said first epitaxial layer but remaining less than the impurity concentration of said first epitaxial layer.
Claim 7
Independent Claim
52 words
The method according to claims 2 or 3 wherein said first epitaxial layer is formed to have an impurity concentration in the order of 10 17 atoms per cubic centimeter and said second epitaxial layer is formed to have an impurity concentration in the order of 10 15 atoms per cubic centimeter.
Claim 8
Dependent Claim
70 words
The method according to claim 1 wherein said depositing of P conductivity type impurities at the surface of said first layer is performed nonselectively to form a P conductivity type impurity layer on said first epitaxial layer; and including diffusing N conductivity type impurities from the surface of said second epitaxial layer down into said first epitaxial layer through said P conductivity type buried layer to form a guard ring.
Claim 9
Dependent Claim
72 words
The method according to claim 1 wherein said depositing of P conductivity type impurities at the surface of said first layer is performed selectively to form a P conductivity type impurity region in said surface, and including diffusing N conductivity type impurities from the surface of said second epitaxial layer to at least the depth of the top of said up-diffusing buried region to form a guard ring around said buried region.
Claim 10
Dependent Claim
21 words
The method according to claim 5 or 6 wherein said N conductivity type impurities diffusion is performed during said simultaneous diffusion.
Claim 11
Dependent Claim
37 words
The method according to claim 1 including depositing N type impurities at the surface of said second layer to the order of 10 19 atoms per cubic centimeter to form shallow ohmic contact to said second layer.
Claim 12
Independent Claim
208 words
A method of fabricating a complementing pair of inverse vertically aligned PNP and NPN transistors comprising: epitaxially forming a first N conductivity type layer on a P conductivity type substrate having a lower impurity concentration than said substrate; depositing P type impurities on a surface of said first epitaxial layer having an impurity concentration lower than said first layer; epitaxially forming a second N conductivity type layer on said first epitaxial layer having a bulk resistivity an order of magnitude less than the bulk resistivity of said first epitaxial layer; depositing P conductivity type impurities into the surface of said second epitaxial layer to define a base ring; depositing N conductivity type impurities into said surface of said second epitaxial layer to define a guard ring; and simultaneously diffusing said deposited impurities to form an up-diffused, buried P type region connected to the surface of said second epitaxial layer by a P type base ring and to form an N type guard ring; said substrate, said first epitaxial layer and said buried region constitute the emitter, base and collector, respectively of said PNP transistor and said first epitaxial layer, said buried region and said second epitaxial layer consitute the emitter, base and collector of said NPN transistor, respectively.
Claim 13
Independent Claim
208 words
A method of fabricating a complementing pair of inverse vertically aligned PNP and NPN transistors comprising: epitaxially forming a first N conductivity type layer on a P conductivity type substrate having a lower impurity concentration than said substrate; depositing P type impurities on a surface of said first epitaxial layer having an impurity concentration lower than said first layer; epitaxially forming a second N conductivity type layer on said first epitaxial layer having a bulk resistivity an order of magnitude less than the bulk resistivity of said first epitaxial layer; depositing P conductivity type impurities into the surface of said second epitaxial layer to define a base ring; depositing N conductivity type impurities into said surface of said second epitaxial layer to define a guard ring; and simultaneously diffusing said deposited impurities to form an up-diffused, buried P type region connected to the surface of said second epitaxial layer by a P type base ring and to form an N type guard ring; said substrate, said first epitaxial layer and said buried region constitute the emitter, base and collector, respectively of said PNP transistor and said first epitaxial layer, said buried region and said second epitaxial layer consitute the emitter, base and collector of said NPN transistor, respectively.
Claim 14
Dependent Claim
55 words
The method according to claim 9 wherein said P conductivity type impurities are nonselectively deposited on said first epitaxial layer and said N conductivity type guard ring is diffused from said surface of said second epitaxial layer down into said first epitaxial layer beyond the junction of said buried region and said first epitaxial layer.
Claim 15
Dependent Claim
78 words
The method according to claim 9 wherein said P conductivity type impurities are deposited at the surface of said first layer and upwardly diffused to form said buried region having an impurity concentration equal to the impurity concentration of said second epitaxial layer at the junction therebetween and said buried layer impurity concentration increasing toward the junction of said buried region and said first epitaxial layer, but remaining less than the impurity concentration of said first epitaxial layer.
Claim 16
Dependent Claim
30 words
The method according to claim 9 including depositing a shallow region of N type impurities at the surface of said second layer to form ohmic contact to said second layer.
References Cited (Backward Citations)
US3823353A
Cited
US3922565A
Cited
US3961351A
Cited
US3916218A
Cited
US3909807A
Cited
US4081697A
Cited
US4051506A
Cited
US4106049A
Cited
US4140559A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-23 | 1984-06-23 | 1984-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-23 | 1988-06-23 | 1988-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-23 | 1992-06-23 | 1992-12-23 | $7700.00 | Window Closed / Lapsed |