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US4232328A
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Dielectrically-isolated integrated circuit complementary transistors for high voltage use
Assignee: AT&T Inc
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Filing: 1978-12-20
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Granted: 1980-11-04
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Expires: 1998-12-20
Abstract
Abstract Integrated circuit complementary transistors for high voltage switching applications are fabricated in separate dielectrically-isolated pockets (12), (14) of high resistivity silicon, supported in a conductive medium (11) such as polycrystalline silicon, using surface adjacent conductivity type zones constituting emitter (19), (23), base (16), (20) and collector zones (17), (21). In one embodiment using high resistivity (75-300 ohm cm) silicon, referred to as π material, for the material of the pocket, one transistor is a PNπP device, and the other is an NPπN. In the PNπP the reverse-biased base-collector pn junction is the interface between the N base zone (16) and the π portion (12) of the collector zone. In the NPπN transistor the base-collector junction is the interface between the lightly doped π extension (14) of the base zone (20) and the N collector zone (21). A connection (32) is provided to the conductive substrate to enable application of a suitable potential thereto.
Inventors
- 👤 Adrian R. Hartman
- 👤 Terence J. Riley
- 👤 Peter W. Shackle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:06
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
115 words
A composite semiconductor device 10 for a high voltage integrated circuit having a plurality of pockets 12, 14 of monocrystalline semiconductor material of P conductivity type dielectrically isolated from each other by a layer of insulating material 13, 15 underlying the bottom and sides thereof, said pockets being supported in a layer 11 of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that (a) there is a first pocket 12 containing a pnπp transistor and a second pocket 14 containing a npπn transistor, and (b) the semiconductor material of said pockets has a resistivity in the range of from about 75 ohm cm to about 300 ohm/cm.
Claim 2
Dependent Claim
115 words
A composite semiconductor device 10 for a high voltage integrated circuit having a plurality of pockets 12, 14 of monocrystalline semiconductor material of P conductivity type dielectrically isolated from each other by a layer of insulating material 13, 15 underlying the bottom and sides thereof, said pockets being supported in a layer 11 of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that (a) there is a first pocket 12 containing a pnπp transistor and a second pocket 14 containing a npπn transistor, and (b) the semiconductor material of said pockets has a resistivity in the range of from about 75 ohm cm to about 300 ohm/cm.
Claim 3
Dependent Claim
103 words
A composite semiconductor device for a high voltage integrated circuit having a plurality of pockets of monocrystalline semiconductor material of n conductivity type dielectrically isolated from each other by a layer of insulating material underlying the bottom and sides thereof, said pockets being supported in a layer of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that: (a) there is a first pocket containing a pnνp transistor and a second pocket containing a npνn transistor, and (b) the semiconductor material of said pockets has a resistivity at least on the order of 75 ohm cm.
Claim 4
Dependent Claim
103 words
A composite semiconductor device for a high voltage integrated circuit having a plurality of pockets of monocrystalline semiconductor material of n conductivity type dielectrically isolated from each other by a layer of insulating material underlying the bottom and sides thereof, said pockets being supported in a layer of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that: (a) there is a first pocket containing a pnνp transistor and a second pocket containing a npνn transistor, and (b) the semiconductor material of said pockets has a resistivity at least on the order of 75 ohm cm.
Claim 5
Dependent Claim
51 words
A semiconductor device in accordance with claim 1 or 2 in which the pockets of semiconductor material have a depth from the common plane surface of from about 30 to about 50 microns and said insulating layer is silicon oxide having a thickness of from about 1.5 to about 5 microns.
Claim 6
Dependent Claim
25 words
A semiconductor device in accordance with claim 3 in which the polycrystalline semiconductor layer 11 has a resistivity of the order of 100 ohm cm.
Claim 7
Dependent Claim
147 words
A composite semiconductor device for a high voltage integrated circuit having a plurality of pockets of monocrystalline semiconductor material of a first conductivity type dielectrically isolated from each other by a layer of insulating material underlying the bottom and sides thereof, said pockets being supported in a layer of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that: (a) the semiconductor material of said pockets is p-type conductivity having a resistivity in the range of from about 75 ohm cm to about 300 ohm cm and is of substantially uniform purity distribution, (b) there is a first pocket containing a pnπp transistor and a second pocket containing a npπn transistor, (c) the layer of polycrystalline material is n-type conductivity silicon having a resistivity of the order of 100 ohm cm and includes contacting means for applying a potential thereto.
Claim 8
Dependent Claim
147 words
A composite semiconductor device for a high voltage integrated circuit having a plurality of pockets of monocrystalline semiconductor material of a first conductivity type dielectrically isolated from each other by a layer of insulating material underlying the bottom and sides thereof, said pockets being supported in a layer of polycrystalline semiconductor material and having a surface in a common plane of said device, Characterized in that: (a) the semiconductor material of said pockets is p-type conductivity having a resistivity in the range of from about 75 ohm cm to about 300 ohm cm and is of substantially uniform purity distribution, (b) there is a first pocket containing a pnπp transistor and a second pocket containing a npπn transistor, (c) the layer of polycrystalline material is n-type conductivity silicon having a resistivity of the order of 100 ohm cm and includes contacting means for applying a potential thereto.
Claim 9
Dependent Claim
37 words
A semiconductor device in accordance with claim 5 in which said pockets have a depth of from about 30 to about 50 microns and said insulating layer has a thickness of from about 1.5 to 5 microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-04 | 1984-05-05 | 1984-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-04 | 1988-05-05 | 1988-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-04 | 1992-05-05 | 1992-11-04 | $7700.00 | Window Closed / Lapsed |