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US4225947A
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Three phase line-addressable serial-parallel-serial storage array
Assignee: International Business Machines Corp
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Filing: 1978-12-29
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Granted: 1980-09-30
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Expires: 1998-12-29
Abstract
Abstract Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.
Inventors
- 👤 Edwin D. Councill
- 👤 H. Janet Kelly
- 👤 Hua-Tung Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/891; G; G11; G11C; G11C19/00; G11C19/28; G11C19/287
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
244 words
A controlled three phase line-addressable serial-parallel-serial storage array comprising: a serial input register for accepting data bits at an input; a serial output register for providing data bits at an output; a parallel register having a plurality of parallel columns, each said column arranged between a storage position in said input register and a storage position in said output register, for receiving data bits from said serial input register and for transferring data bits to said serial output register; first, second, and third phase lines connected to each said registers; and control lines connected to each said registers, each one of said control lines being adapted to selectively inhibit the propagation of data bits in said registers; the first, second, and third phase lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said columns, each said first, second and third phase lines being associated with one row of said parallel register; the control lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said first, second, and third phase lines, each said control lines extending along one of the columns of the parallel register such that a control signal applied by means of one or more of said control lines to a desired one or more of the columns selectively inhibits or permits data bit propagation from one row of said parallel register to another along said one or more columns.
Claim 2
Dependent Claim
244 words
A controlled three phase line-addressable serial-parallel-serial storage array comprising: a serial input register for accepting data bits at an input; a serial output register for providing data bits at an output; a parallel register having a plurality of parallel columns, each said column arranged between a storage position in said input register and a storage position in said output register, for receiving data bits from said serial input register and for transferring data bits to said serial output register; first, second, and third phase lines connected to each said registers; and control lines connected to each said registers, each one of said control lines being adapted to selectively inhibit the propagation of data bits in said registers; the first, second, and third phase lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said columns, each said first, second and third phase lines being associated with one row of said parallel register; the control lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said first, second, and third phase lines, each said control lines extending along one of the columns of the parallel register such that a control signal applied by means of one or more of said control lines to a desired one or more of the columns selectively inhibits or permits data bit propagation from one row of said parallel register to another along said one or more columns.
Claim 3
Dependent Claim
83 words
A controlled three phase line-addressable serial-parallel-serial storage array as in claim 1, wherein: each one of said first, second, and third phase lines are connected to corresponding ones of a plurality of gate electrodes along each row of said parallel register; each one of said control lines being connected to a corresponding one of a plurality of control gate electrodes along each one of said columns in said parallel register; each one of said gate electrodes being formed from a polycrystalline silicon material.
Claim 4
Dependent Claim
30 words
A controlled three phase line-addressable serial-parallel-serial storage array as in claim 2, wherein: alternate ones of said gate electrodes are formed from first and second levels of polycrystalline silicon material.
Claim 5
Dependent Claim
55 words
A controlled three phase line-addressable serial-parallel-serial storage array as in claim 3 wherein: the control gate electrodes associated with each said control lines are formed from the second level of polycrystalline silicon material and are adapted to be dimensioned smaller than any of the gate electrodes associated with the first, second and third phase lines.
Claim 6
Dependent Claim
42 words
A controlled three phase line-addressable serial-parallel-serial storage array as in claim 1 further comprising: means for selectively connecting a desired one or more of said control lines to either a fixed potential or to one of said first, and third phase lines.
Claim 7
Dependent Claim
24 words
A controlled three phase line-addressable serial-parallel-serial storage array as in claim 5 wherein the control line is selectively connectable to said third phase line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-30 | 1984-03-31 | 1984-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-30 | 1988-03-31 | 1988-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-30 | 1992-03-31 | 1992-09-30 | $7700.00 | Window Closed / Lapsed |