Storage arrangement with modules consisting of CCD stores

Claim 2

A storage arrangement suited for use with CCD stores comprising a CCD storage area having a series-parallel-series arrangement of data flow in which 2 m parallel shift registers each of length n bits are arranged between an input shift register and an output shift register each being of length m bits; said 2m parallel shift registers being constructed with one storage electrode for each storage location using the electrode-per-bit principle; a circular pulse train shift register having a length of n storage locations with said n bits of said circular pulse train shift register each being connected to the gate termial of one of n switching transistors, each of said switching transistors having a first input connected to a supply potential and a second input connected to one of n pulse train lines of said storage area; a circulating charge in said circular shift register being the means whereby each one of said n switching transistors cyclically connects one of said n pulse train lines to said supply potential.

Claim 3

A storage arrangement according to claim 1, wherein said pulse train shift register comprises a CCD shift register with each second storage electrode possessing a diffusion zone in the substrate; the control electrodes of a first and second switching transistor being connected to said diffusion zone, a first input to said first transistor being connected to a first of said pulse train lines and a first input to said second transistor being connected to a second of said pulse train lines; said first and second pulse train lines being successively connected to said storage area; a second input of said first transistor being connected to a reference potential and a second input of said second transistor being connected to a supply potential; said first and second transistors being operated in a push-pull mode whereby when said first transistor conducts and connects said reference potential to said first previously charged pulse train line discharging said first pulse train line said second transistor conducts and connects said supply potential to said second pulse train line charging said second pulse train line.

Claim 4

The storage arrangement according to claim 2, wherein said pulse train shift register comprises shift register having each of the diffusion zones arranged beneath the silicon part of the storage electrode.

Claim 5

The storage arrangement according to claim 2, wherein said pulse train shift register comprises a shift register having each of the diffusion zones arranged beneath the aluminum part of the storage electrode.

Claim 6

The storage arrangement according to claim 1, wherein said pulse train shift register comprises a four-phase MOS shift register such that each storage location has a first inverter with an output connected to the input of a second inverter; said first and second inverters each having three MOS transistors arranged in series between a reference potential and a ground potential; the output of said second inverter being connected to the control electrode of a control transistor; said control transistor having a first input connected to a source of control potential and a second input connected to one of said pulse train lines of said storage area.

Claim 7

A storage arrangement according to one of claims 1 the storage area comprising at least two storage areas each having a series-parallel-series arrangement of data flow and each operating in accordance with the electrode-per-bit principle.

Claim 8

A storage arrangment according to claim 6, said storage means being arranged one beneath the other and said pulse train shift register having one circulating charge for each of said storage areas; said circulating charges being spaced to properly switch said n pulse train lines.

Claim 9

The storage arrangement according to claim 7, said storage areas being arranged beneath one another and parallel to one another and said pulse train lines being through-connected transversely across said parallel storage areas.

Claim 10

A storage arrangement suited for use with CCD stores comprising a CCD storage area having a series-parallel-series arrangement of data flow in which 2m parallel shift registers each of length n bits are arranged between an input shift register and an output shift register each being of length m bits; said 2m parallel shift registers being constructed with one storage electrode for each storage location using the electrode-per-bit principle; a circular pulse train shift register having a length of n storage locations with said n bits of said circular pulse train shift register each being connected to the gate terminal of one of n switching transistors, each of said switching transistors having a first input connected to a supply potential and a second input connected to one of n pulse train lines of said storage area; a circulating charge in said circular shift register being the means whereby each one of said n switching transistors cyclically connects one of said n pulse train lines to said supply potential, said pulse train shift register comprising a CCD shift register with each second storage electrode possessing a diffusion zone in the substrate; the control electrodes of a first and second switching transistor being connected to said diffusion zone, a first input to said first transistor being connected to a first of said pulse train lines and a first input to said second transistor being connected to a second of said pulse train lines; said first and second pulse train lines being successively connected to said storage area; a second input of said first transistor being connected to a reference potential and a second input of said second transistor being connected to a supply potential; said first and second transistors being operated in a push-pull mode whereby when said first transistor conducts and connects said reference potential to said first previously charged pulse train line discharging said first pulse train line said second transistor conducts and connects said supply potential to said second pulse train line charging said second pulse train line.

Claim 11

A storage arrangement suited for use with CCD stores comprising a CCD storage area having a series-parallel-series arrangement of data flow in which 2m parallel shift registers each of length n bits are arranged between an input shift register and an output shift register each being of length m bits; said 2m parallel shift registers being constructed with one storage electrode for each storage location using the electrode-per-bit principle; a circular pulse train shift register having a length of n storage locations with said n bits of said circular pulse train shift register each being connected to the gate terminal of one of n switching transistors, each of said switching transistors having a first input connected to a supply potential and a second input connected to one of n pulse train lines of said storage area; a circulating charge in said circular shift register being the means whereby each one of said n switching transistors cyclically connects one of said n pulse train lines to said supply potential, said pulse train shift register comprising a CCD shift register with each second storage electrode possessing a diffusion zone in the substrate; the control electrodes of a first and second switching transistor being connected to said diffusion zone, a first input to said first transistor being connected to a first of said pulse train lines and a first input to said second transistor being connected to a second of said pulse train lines; said first and second pulse train lines being successively connected to said storage area; a second input of said first transistor being connected to a reference potential and a second input of said second transistor being connected to a supply potential; said first and second transistors being operated in a push-pull mode whereby when said first transistor conducts and connects said reference potential to said first previously charged pulse train line discharging said first pulse train line said second transistor conducts and connects said supply potential to said second pulse train line charging said second pulse train line.

Claim 12

A storage arrangement according to claim 9, the storage area comprising at least two storage areas each having a series-parallel-series arrangement of data flow and each operating in accordance with the electrode-per-bit principle.