Three phase charge-coupled device memory with inhibit lines

Claim 2

A charge coupled device shift register memory structure activatable by a plurality of clock phases produced by a clock generator comprising: a plurality of charge coupled device shift register channels for storing data bits in the form of charge packets; a thin dielectric layer disposed over each said channel; a plurality of parallel gate electrode means disposed perpendicular to said channels upon said dielectric layer for shifting said data bits in said channel in response to said clock phases; and means for selectively varying the potential between said plurality of gate electrode means with respect to selected of said shift register channels, for selectively inhibiting or aiding the said clock shifting of said data bits in response to the potential presented by said potential varying means.

Claim 3

The memory structure of claim 1 wherein said selectively varying potential means includes: a second dielectric layer overlying said gate electrode means; and a plurality of potential varying lines, each disposed upon said second dielectric layer and over a respective shift register channel.

Claim 4

The memory structure of claim 2 wherein said parallel gate electrode means are separated by a distance greater than 0.1 mil.

Claim 5

The memory structure of claim 3 wherein said dielectric layers are silicon dioxide, said gate electrodes are polysilicon and each of said potential varying lines is aluminum.

Claim 6

The memory structure of claim 1 and further activatable in response to read and write control signals, at least one refresh indicating signal and an access address presenting a particular selected shift register channel which is to be accessed via said potential varying means and further including: commonly connected output means for each said shift register channel; commonly connected input means for each said shift register channel; decoding means for decoding said access address to vary said potential by said potential varying means in the said particular shift register channel represented by said access address, to perform access thereof; and means receiving an input from said commonly connected output means for gating data bits in said particular selected shift register channel out of said memory structure in response to a said read control signal and from said commonly connected output means to said commonly connected input means in response to said at least one refresh indicating signal and for gating data bits into said particular selected channel in response to a write control signal.

Claim 7

The memory structure of claim 5 wherein said potential varying means comprises: a second dielectric layer overlying said gate electrode means; and a plurality of potential varying lines, each disposed upon said second dielectric layer and over a said shift register channel.

Claim 8

The memory structure of claim 6 wherein said access address includes a refresh address and a read/write address and said decoding means comprises: a channel decoder for decoding said refresh and read/write addresses, said decoder having an input and an output connected to each of said potential varying lines; a refresh address counter for developing a plurality of said refresh addresses; and address gate means for gating each said refresh address and each said read/write address to the input of said channel decoder.