Recursive digital filter having means to prevent overflow oscillation

Claim 2

A recursive digital filter comprising: (a) first means to which an m-bit digital input signal x(n) is applied, (b) calculating means having an input and an output means, said input means connected to said first means, for delivering from said output means thereof a digital signal y(n) shown by a formula, ##EQU9## where n represents a natural number, N and M are orders representing a delay of signal transmission, and a k and b k are coefficients with a M , b N ≠0, and N≧2, (c) second means including first and second delay means connected in series, said second means being connected between the output means and the input means of said calculating means for delaying an m-bit signal of said digital signal y(n) by two sampling periods or more from said input signal x(n) and for feeding back the delayed signal to the input means of said calculating means, (d) overflow detector means connected to the output means of said calculating means and to the first and second delay means of said second means, for supplying a signal for setting the contents of both said first and second delay means into a specified state when the value of said digital signal y(n) exceeds a predetermined value, and (e) third means coupled to said first delay means of said second means for delivering an m-bit digital signal y(n) as the output of the filter.

Claim 3

A recursive digital filter according to claim 1, wherein said first means includes at least third delay means connected to the input of said calculating means, said input signal x(n) being supplied directly to the input of said calculating means and at the same time supplied to the input of said calculating means through said third delay means which delays said input signal x(n) by k sampling periods.

Claim 4

A recursive digital filter according to claim 2, wherein the third delay means is a register.

Claim 5

A recursive digital filter according to claim 2, wherein said third delay means is connected with said overflow detector, thereby to set the contents of said third delay means into a specified state when the value of said signal y(n) exceeds a predetermined value.

Claim 6

A recursive digital filter according to claim 1, 2, or 3, wherein said specified state is zero.

Claim 7

A recursive digital filter according to claim 1, 2, or 3, wherein said calculating means comprises: (a) said input means for said calculating means comprising a data storage means, coupled to said first means and said second means to allow data to be read out therefrom by addressing said data storage means with input and output signals x(n-k) and y(n-k), respectively, and (b) summation means coupled to an output of said data storage means for summing the outputs of said data storage means at every sampling period thereby to output digital data y(n), which is parallel data, made up of more than m-bits, the m-bits of said digital data y(n) being supplied to said first delay means which converts the m-bit parallel data into a serial data.

Claim 8

A recursive digital filter according to claim 6, wherein said data storage means comprises a read only memory.

Claim 9

A recursive digital filter comprising: (a) an input terminal into which an m-bit digital input signal x(n) is applied; (b) an output terminal for delivering a digital signal y(n); (c) calculating means, connected between said input terminal and said output terminal, for converting said input signal x(n) into said signal y(n) which satisfies, ##EQU10## where n represents a natural number, M and N are orders representing a delay of signal transmission, and a k and b k are coefficients with a M , b N ≠0, and N≧2, said calculating means including, (1) first and second delay means connected in series to each other, each of which has an m-bit data capacity, (2) first multiplier means, connected to said second delay means, for multiplying the output signal of said second delay means by a first coefficient b k , (3) first summation means, connected between said input terminal and the output of said first multiplier means, for adding at least said input signal x(n) and the output signal of said first multiplier means and coupled to the first delay means for supplying the output thereof to said first delay means, (4) second multiplier means, connected to said first summation means, for multiplying the output signal of said first summation means by a second coefficient a0, (5) third multiplier means, connected to said second delay means, for multiplying the output signal of said second delay means by a third coefficient a k , and (6) second summation means, connected between said second and third multiplier means, for adding at least the output signal of said second multiplier means and the output signal of said third multiplier means, and coupled to the output terminal for supplying the output of the second summation means to said output terminal; and (d) an overflow detector, connected to said first summation means and said first and second delay means for supplying a signal for setting the contents of said first and second delay means into a specified state when the value of the output signal of said first summation means exceeds a predetermined value.

Claim 10

A recursive digital filter comprising: (a) an input terminal into which an m-bit digital input signal x(n) is applied; (b) an output terminal for delivering a digital signal y(n); (c) calculating means, connected between said input terminal and said output terminal, for converting said input signal x(n) into said signal y(n) which satisfies, ##EQU10## where n represents a natural number, M and N are orders representing a delay of signal transmission, and a k and b k are coefficients with a M , b N ≠0, and N≧2, said calculating means including, (1) first and second delay means connected in series to each other, each of which has an m-bit data capacity, (2) first multiplier means, connected to said second delay means, for multiplying the output signal of said second delay means by a first coefficient b k , (3) first summation means, connected between said input terminal and the output of said first multiplier means, for adding at least said input signal x(n) and the output signal of said first multiplier means and coupled to the first delay means for supplying the output thereof to said first delay means, (4) second multiplier means, connected to said first summation means, for multiplying the output signal of said first summation means by a second coefficient a0, (5) third multiplier means, connected to said second delay means, for multiplying the output signal of said second delay means by a third coefficient a k , and (6) second summation means, connected between said second and third multiplier means, for adding at least the output signal of said second multiplier means and the output signal of said third multiplier means, and coupled to the output terminal for supplying the output of the second summation means to said output terminal; and (d) an overflow detector, connected to said first summation means and said first and second delay means for supplying a signal for setting the contents of said first and second delay means into a specified state when the value of the output signal of said first summation means exceeds a predetermined value.

Claim 11

A recursive digital filter according to claim 1 or 8, wherein the first and second delay means are registers.