Complementary semiconductor device

Claim 1

A complementary semiconductor device comprising a semiconductor substrate of one conductivity type having a low impurity concentration; P -and N-type semiconductor regions formed in said substrate and having substantially the same impurity concentration; an N-channel type silicon gate field effect transistor including source and drain regions formed in said P-type semiconductor region and a gate region including a gate electrode comprising a polycrystalline silicon layer of one conductivity type; a P-channel type silicon gate field effect transistor including source and drain regions formed in said N-type semiconductor region and a gate region including a gate electrode comprising a polycrystalline silicon layer, said polycrystalline silicon layer being of the same conductivity type as that of said polycrystalline silicon layer of said N-channel transistor; a first impurity layer formed in that portion of the P-type semiconductor region which corresponds to said gate region and determining the threshold voltage of said N-channel transistor; and a second impurity layer formed in that portion of the N-type semiconductor region which corresponds to said gate region and determining the threshold voltage of said P-channel transistor, said second impurity layer being formed by doping the same conductivity type impurity as that of said first impurity layer.