Patent US4199778A successfully refreshed from Google Patents.
US4199778A
Expired / Lapsed
US
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Interconnection structure for semiconductor integrated circuits
Assignee: Hitachi Ltd
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Filing: 1977-10-19
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Granted: 1980-04-22
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Expires: 1997-10-19
Abstract
Abstract In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.
Inventors
- 👤 Toshiaki Masuhara
- 👤 Tokumasa Yasui
- 👤 Yoshio Sakai
- 👤 Joh Nakajima
- 👤 Yasunobu Kosa
- 👤 Satoshi Meguro
- 👤 Masaharu Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:42
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/40; H10W20/41; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
142 words
An interconnection structure for a semiconductor integrated circuit, comprising: a semiconductor substrate, a first insulating film which is provided on said semiconductor substrate, low resistance polycrystalline silicon interconnections which have a predetermined pattern and which are provided on said first insulating film, a high resistance polycrystalline silicon layer which has substantially the same height as that of said low resistance polycrystalline silicon interconnections and which is provided on said first insulating film, in contact with the low resistance polycrystalline silicon interconnections, and in at least regions surrounding through-holes, a second insulating film which is provided so as to cover the low resistance polycrystalline silicon layer and said high resistance polycrystalline silicon layer except said through-holes, and metal interconnections which are provided on said second insulating film and which lie in electrical contact with said low resistance polycrystalline silicon interconnections through said through-holes.
Claim 2
Dependent Claim
142 words
An interconnection structure for a semiconductor integrated circuit, comprising: a semiconductor substrate, a first insulating film which is provided on said semiconductor substrate, low resistance polycrystalline silicon interconnections which have a predetermined pattern and which are provided on said first insulating film, a high resistance polycrystalline silicon layer which has substantially the same height as that of said low resistance polycrystalline silicon interconnections and which is provided on said first insulating film, in contact with the low resistance polycrystalline silicon interconnections, and in at least regions surrounding through-holes, a second insulating film which is provided so as to cover the low resistance polycrystalline silicon layer and said high resistance polycrystalline silicon layer except said through-holes, and metal interconnections which are provided on said second insulating film and which lie in electrical contact with said low resistance polycrystalline silicon interconnections through said through-holes.
Claim 3
Dependent Claim
22 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein said low resistance polycrystalline silicon interconnections are p-conductivity type.
Claim 4
Dependent Claim
54 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein both said substrate and said low resistance polycrystalline silicon interconnections are n-conductivity type, and a p-conductivity type layer is provided in a surface region of said substrate lying in contact with said first insulating film, said p-conductivity type layer being grounded.
Claim 5
Dependent Claim
27 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein said high resistance polycrystalline silicon layer has a sheet resistance of above 100 KΩ/□.
Claim 6
Dependent Claim
30 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein said low resistance polycrystalline silicon interconnections have an impurity concentration of above 1×10 19 atoms/cm 3 .
Claim 7
Dependent Claim
35 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein said low resistance polycrystalline silicon interconnections and said high resistance polycrystalline silicon layer cover the whole surface of said first insulating film.
Claim 8
Dependent Claim
28 words
An interconnection structure for a semiconductor integrated circuit according to claim 1, wherein said high resistance polycrystalline silicon layer is provided only in the regions surrounding said through-holes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-22 | 1983-10-22 | 1984-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-22 | 1987-10-22 | 1988-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-22 | 1991-10-22 | 1992-04-22 | $7700.00 | Window Closed / Lapsed |