Self biasing of a field effect transistor mounted in a flip-chip carrier

Claim 1

A circuit that includes a field effect transistor having pluralities of unit gates, unit drains and unit sources disposed upon a substrate, said unit sources being plated with an electrically conductive material to form posts on said unit sources with distal surfaces having a displacement from said substrate greater than the displacement of the distal surfaces of said unit gates and said unit drains from said substrate, said distal ends of said posts being in contact with the top surface of a flip-chip carrier, the improvement comprising: a block of an electrically insulating material having a thermal resistance that approximates the thermal resistance of brass; a metal plate having first and second surfaces in contact with one surface of said block and the bottom surface of said carrier, respectively, whereby said plate is between said block and said carrier; a metal sheet formed for contact with said one surface of said block and a surface of said block opposed therefrom, said sheet extending over said one surface of said block sufficiently only to provide a gap for a discontinuity in the electrical conduction path through said metal sheet and said metal plates; a block of brass having one surface in thermal and electrical contact with said opposed surface of said metal sheet, said block serving as the ground plane of said circuit; and a film resistor disposed upon said block between said gap and on the surface of said insulating block, said resistor connecting said metal plate and said metal sheet to provide thereby an electrical resistance between said unit sources for self-biasing said transistor whereby said unit sources are thermally coupled by the low thermal resistance path formed by said metal plate, said metal sheet and said insulating and brass blocks.