Hybrid transistor

Abstract

Abstract A HYBRID TRANSISTOR COMPRISING A TRANSISTOR DIE AND INTERNALLY DISPOSED CAPACITIVE ELEMENTS CONFIGURED TO REDUCE SUBSTANTIALLY THE INDUCTANCE OF THE TRANSISTOR''S INPUT, TYPICALLY THE BASE IN COMMON EMITTER CONFIGURATIONS, WHILE AT THE SAME TIME PROVIDING A BUILT-IN FIRST STAGE NETWORK FOR BROAD-BAND IMPEDANCE MATCHING AND IMPEDANCE TRANSFORMATION. IN A BASIC EMBODIMENT OF THIS INVENTION, THE TRANSISTOR DIE IS DISPOSED UPON A COMMON METALLIZED AREA OF A TRANSISTOR PACKAGE. TYPICALLY, THE COLLECTOR REGIONS ARE IN ELECTRICAL CONTACT WITH THIS METAL LIZED AREA. RELATIVELY SHORT AND UNIFORM BASE LEAD BONDS CONNECT EACH OF PLURALITY OF BASE REGIONS TO ONE SIDE OF AN ARRAY OF CORORESPONDING CAPACITORS DISPOSED UPON A SECOND METALLIZED AREA WHICH SERVES AS THE COMMON EMITTER. THE SECOND SIDES OF THE CAPACITORS ARE IN CONTACT WITH THE COMMON EMITTER AREA. THE EMITTER REGIONS OF THE TRANSISTOR DIE ARE LIKEWISE CONNECTED TO THE COMMON EMITTER AREA THROUGH RELATIVELY SHORT AND UNIFORM LEAD BONDS. IN A PREFERRED EMBODIMENT OF THE PRESENT INVENTION, ADDITIONAL LEAD BONDS ALSO CONNECT THE EMITTER REGIONS TO THE COMMON EMITTER SIDE OF THE CAPACITOR ARRAY. BY MAKING THE LATTER EMITTER LEAD BONDS OF THE SAME LENGTH AND CONTOUR AS THE BASE LEAD BONDS, AND BY INTERLEAVING THEM IN PARALLEL WITH THE BASE LEAD BONDS, A FURTHER REDUCTION OF THE INPUT INDUCTANCE OF THE INVENTED HYBRID TRANSISTOR IS ACHIEVED. THE PRESENT INVENTION DISCLOSES A TRANSISTOR HAVING SUPERIOR HIGH FREQUENCY OPERATING CHARACTERISTICS THAN HERETOFORE ATTAINABLE AT POWER LEVELS IN EXCESS OF 40 WATTS. THE SUPERIOR OPERATING CHARACTERISTICS, INCLUDING LOW INPUT INDUCTANCE AND LOW IMPEDANCE TRANSFORMATION, ENABLE BROAD-BAND UNIFORM AMPLICATION OVER AS MUCH AS ONE OCTAVE OF THE FREQUENCY BAND ABOVE 100 MHZ.

Inventors

• 👤 E Rice
• 👤 T Litty
• 👤 E Moss

Bibliographic Details