Logic circuits incorporating a dual function input

Claim 2

A logic circuit comprising: (a) first input means for receiving a digital signal, the digital signal having at least three discrete logic levels; (b) second input means for receiving at least one binary signal; (c) at least one enabling means coupled to said first input means and responsive to the digital signal for generating at least one enable signal; and (d) logic means coupled to said first and second input means and responsive to the digital signal and to the at least one binary signal for selectively generating a binary output signal representative of one of a plurality of logic functions, said logic means being responsive to the at least one enable signal for determining which logic function of the plurality of logic functions is represented by the binary output signal.

Claim 3

A logic circuit as recited in claim 1 wherein said at least one enabling means comprises first semiconductor switching means coupled to said first input means and responsive to the digital signal for causing the at least one enable signal to indicate an occurrence of the digital signal being in a first logic level among the at least three discrete logic levels.

Claim 4

A logic circuit as recited in claim 2 wherein said first semiconductor switching means is adapted to receive a reference signal, said first semiconductor switching means being operative to compare the digital signal to the reference signal in order to detect an occurrence of the digital signal being in the first logic level.

Claim 5

A logic circuit as recited in claim 2 wherein said logic means includes second semiconductor switching means coupled to first input means and responsive to the digital signal for generating at least one of the plurality of logic functions, said second semiconductor switching means being operative to detect a transition of the digital signal between a second logic level and at least a third logic level among the at least three logic levels.

Claim 6

A logic circuit as recited in claim 4 wherein said second semiconductor switching means is adapted to receive a reference signal, said second semiconductor switching means being operative to compare the digital signal to the reference signal in order to detect the transition of the digital signal between the second and at least third logic levels.

Claim 7

A logic circuit as recited in claim 4 wherein said logic means is adapted to select said at least one of the plurality of logic functions generated by said second semiconductor switching means for representation by the binary output signal only when the at least one enable signal indicates that the digital signal is not in the first logic level.

Claim 8

A logic circuit as recited in claim 4 wherein said first and second semiconductor switching means each comprise differentially coupled transistor switches.

Claim 9

A logic circuit as recited in claim 4 wherein said first and second semiconductor switching means each comprise emitter-coupled logic circuits.

Claim 10

A logic circuit comprising: (a) first means for receiving a digital signal, the digital signal having at least three logic levels; (b) first switching means for implementing a first binary logic function, said first switching means being coupled to said first means and being responsive to the digital signal such that the first binary logic function is dependent upon whether the digital signal is in a first or in a second logic level; (c) second switching means for implementing a second binary logic function, said second switching means being responsive to at least one binary input signal, the second binary logic function being independent of the digital signal; (d) enable means coupled to said first means and responsive to the digital signal for generating an enable signal, said enable means being effective to discern the first and second logic levels of the digital signal from at least a third logic level of the digital signal such that the enable signal is in a first state when the digital signal is in the first or second logic levels and in a second state when the digital signal is in the at least third logic level; and (e) output means coupled to said first and second switching means for selectively generating a binary output signal, said output means being responsive to the enable signal such that the binary output signal is representative of the first or second binary logic function in accordance with the enable signal being in the first or second state, respectively.

Claim 11

A logic circuit comprising: (a) first means for receiving a digital signal, the digital signal having at least three logic levels; (b) first switching means for implementing a first binary logic function, said first switching means being coupled to said first means and being responsive to the digital signal such that the first binary logic function is dependent upon whether the digital signal is in a first or in a second logic level; (c) second switching means for implementing a second binary logic function, said second switching means being responsive to at least one binary input signal, the second binary logic function being independent of the digital signal; (d) enable means coupled to said first means and responsive to the digital signal for generating an enable signal, said enable means being effective to discern the first and second logic levels of the digital signal from at least a third logic level of the digital signal such that the enable signal is in a first state when the digital signal is in the first or second logic levels and in a second state when the digital signal is in the at least third logic level; and (e) output means coupled to said first and second switching means for selectively generating a binary output signal, said output means being responsive to the enable signal such that the binary output signal is representative of the first or second binary logic function in accordance with the enable signal being in the first or second state, respectively.

Claim 12

A logic circuit as recited in claim 9 wherein said first and second switching means and said enable means each comprise differentially coupled transistor circuits.