US3818202A
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Binary bypassable arithmetic linear module
Assignee: Unisys Corp
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Filing: 1973-02-20
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Granted: 1974-06-18
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Expires: 1993-02-20
Abstract
Abstract A bypassable module for performing an arithmetic linear function is disclosed. The module utilizes well-known binary elements to construct a novel combination thereof that given three multibit binary input signals C, D, X and the single bit binary input signal b generates the alternative output functions
Inventors
- 👤 J Ellison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/552; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3868; G06F2207/552; G06F2207/5523
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
288 words
A binary bypassable arithmetic linear module, comprising: a binary arithmetic linear module, comprising; a binary multiplier having the binary input signal C as a first input signal and the binary input signal X as a second input signal for generating the binary output signal CX; a first binary adder having the binary input signal D as a first input signal and said binary output signal CX as a second input signal for generating the binary arithmetic linear module output signal CX + D; a binary bypass switch, comprising; a first binary AND gate having said binary arithmetic linear module output signal CX + D as a first input signal and a binary signal b as a second input signal for emitting said binary arithmetic linear module output signal CX + D only if said binary signal b 1; an inverter having said binary signal b as an input signal b for generating an inverter output signal b; a second binary AND gate having said inverter output signAl b as a first input signal and said binary input signal C as a second input signal for emitting said binary input signal C only if said inverter output signal b 1; a binary OR gate having as a first input signal said binary input signal C as emitted from said second binary AND gate and having as a second input signal said binary arithmetic linear module output signal CX + D as emitted from said first binary AND gate for emitting, as the binary bypassable arithmetic linear module output signal, said bindary arithmetic linear module output signal CX + D if said binary signal b 1, or, alternatively, said binary input signal C if said inverter output signal b 1.
Claim 2
Dependent Claim
288 words
A binary bypassable arithmetic linear module, comprising: a binary arithmetic linear module, comprising; a binary multiplier having the binary input signal C as a first input signal and the binary input signal X as a second input signal for generating the binary output signal CX; a first binary adder having the binary input signal D as a first input signal and said binary output signal CX as a second input signal for generating the binary arithmetic linear module output signal CX + D; a binary bypass switch, comprising; a first binary AND gate having said binary arithmetic linear module output signal CX + D as a first input signal and a binary signal b as a second input signal for emitting said binary arithmetic linear module output signal CX + D only if said binary signal b 1; an inverter having said binary signal b as an input signal b for generating an inverter output signal b; a second binary AND gate having said inverter output signAl b as a first input signal and said binary input signal C as a second input signal for emitting said binary input signal C only if said inverter output signal b 1; a binary OR gate having as a first input signal said binary input signal C as emitted from said second binary AND gate and having as a second input signal said binary arithmetic linear module output signal CX + D as emitted from said first binary AND gate for emitting, as the binary bypassable arithmetic linear module output signal, said bindary arithmetic linear module output signal CX + D if said binary signal b 1, or, alternatively, said binary input signal C if said inverter output signal b 1.
Claim 3
Dependent Claim
306 words
A binary bypassable arithmetic linear module, comprising: a multibit binary arithmetic linear module, comprising; a multibit binary multiplier having the multibit binary input signal C as a first input signal and the multibit binary input signal X as a second input signal for generating the multibit binary multiplier multibit binary output signal CX; a first multibit binary adder having the multibit binary input signal D as a first input signal and said multibit binary multiplier multibit binary output signal CX as a second input signal for generating the multibit binary arithmetic linear module multibit binary output signal CX + D; a multibit binary bypass switch, comprising; a first multibit binary AND gate having said multibit binary arithmetic linear module multibit binary output signal CX + D as a first input signal and a single-bit binary signal b as a second input signal for generating the first multibit binary AND gate multibit binary output signal CX + D only if said single-bit binary signal b 1; an inverter having said single-bit binary signal b as an input signal b for generating an inverter single-bit binary output signal b; a second multibit binary AND gate having said inverter single-bit binary output signal b as a first input signal and said multibit binary input signal C as a second input signal for generating the second multibit binary AND gate multibit binary output signal C only if said inverter single-bit binary output signal b 1; a multibit binary OR gate having said second multibit binary AND gate multibit binary output signal C as a first input signal and said first multibit binary AND gate multibit binary output signal CX + D as a second input signal for generating the multibit binary bypassable arithmetic linear module multibit binary output signal C if b 1, or, alternatively, CX + D if b
Claim 4
Dependent Claim
306 words
A binary bypassable arithmetic linear module, comprising: a multibit binary arithmetic linear module, comprising; a multibit binary multiplier having the multibit binary input signal C as a first input signal and the multibit binary input signal X as a second input signal for generating the multibit binary multiplier multibit binary output signal CX; a first multibit binary adder having the multibit binary input signal D as a first input signal and said multibit binary multiplier multibit binary output signal CX as a second input signal for generating the multibit binary arithmetic linear module multibit binary output signal CX + D; a multibit binary bypass switch, comprising; a first multibit binary AND gate having said multibit binary arithmetic linear module multibit binary output signal CX + D as a first input signal and a single-bit binary signal b as a second input signal for generating the first multibit binary AND gate multibit binary output signal CX + D only if said single-bit binary signal b 1; an inverter having said single-bit binary signal b as an input signal b for generating an inverter single-bit binary output signal b; a second multibit binary AND gate having said inverter single-bit binary output signal b as a first input signal and said multibit binary input signal C as a second input signal for generating the second multibit binary AND gate multibit binary output signal C only if said inverter single-bit binary output signal b 1; a multibit binary OR gate having said second multibit binary AND gate multibit binary output signal C as a first input signal and said first multibit binary AND gate multibit binary output signal CX + D as a second input signal for generating the multibit binary bypassable arithmetic linear module multibit binary output signal C if b 1, or, alternatively, CX + D if b
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-17 | 1977-12-17 | 1978-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-17 | 1981-12-17 | 1982-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-17 | 1985-12-17 | 1986-06-18 | $7700.00 | Window Closed / Lapsed |