Signal transmission system with an error control technique

Claim 2

A signal transmission system using a selective automatic repeat request system which comprises a transmission section including first memory means for storing data being transmitted in the form having the prescribed block length measured by a number of bits, control means for selecting a data block having the prescribed serial number from among those which are stored in the memory means, and means connected to the output of the control means for attaching the prescribed check code to the selected data block and for transmitting the code attached data block to a communication channel; and a receiving section including receiving means for receiving a data block sent forth from the transmission section through the communication channel, detection means for detecting an error in a data block received by the receiving means, second memory means connected to the output of the detection means for successively storing only error-free correct data blocks included in the received data blocks, and means which generates an error control signal including a negative acknowledgement information when an erroneous data block is detected by the detection means and which generates no control signal when no erroneous data block is detected by the detection means, said error control signal indicating a demand for retransmission of a new error-free data block corresponding to the previously transmitted data block whose error has been detected by the detection means and said error control signal being transmitted through the communication channel to the control means in the transmission section so that the control means selects the data block corresponding to the error control signal, and wherein the transmission section retransmits a new error-free data block corresponding to an error control signal received from the receiving section, without checking whether the control signal thus received is erroneous or not.

Claim 3

The signal transmission system according to claim 1, wherein the error control signal denotes a data block serial number which is formed of the prescribed number of bits and does not contain an error correction check bit.

Claim 4

The signal transmission system according to claim 1, which further comprises separation means provided in the communication channel for distinguishing between a data block delivered from the transmission section to the receiving section and an error control signal issued from the receiving section to the transmission section.

Claim 5

The signal transmission system according to claim 3, wherein the separation means includes a hybrid type frequency band separator for distinguishing between a data block supplied from the transmission section to the receiving section and an error control signal sent forth from the receiving section to the transmission section, both having different frequency bands.

Claim 6

The signal transmission system according to claim 3, wherein the separation means includes a time sharing circuit designed to change over the operation of the communication channel when a data block is delivered from the transmission section to the receiving section or an error control signal is issued from the receiving section to the transmission section, said operation being continued for a length of time required for transmission of either.

Claim 7

The signal transmission system according to claim 3, wherein the error control signal denotes the prescribed serial number of a data block and does not contain an error correction check bit.

Claim 8

A signal transmission system using a selective automatic repeat request system which comprises a transmission section including first memory means for storing data being transmitted in the form having the prescribed block length measured by a number of bits, control means for selecting a data block having the prescribed serial number from among those which are stored in the memory means connected to the output of the control means, and means for attaching the prescribed check code to the selected data block and for transmitting the code attached data block to a communication channel; and a receiving section including means for receiving a data block delivered from the transmission section through the communication channel, error detection means for judging whether a data block supplied to the receiving section has an error, second memory means connected to the output of the detection means for successively storing only error-free correct data blocks included in those which are conducted to the receiving section, and means which distinguishes between an erroneous data block detected by the detection means and an error-free data block and which generates an error control signal including a negative acknowledgement information when an erroneous data block is detected and no control signal when no erroneous data block is detected, said error control signal indicating a demand for the transmission section to supply the receiving section with a new error-free data block corresponding to said erroneous data block and said error control signal being transmitted through the communication channel to the control means in the transmission section so that the control means selects the data block corresponding to the erroneous data block; and wherein the transmission section retransmits to the receiving section with an error-free data block corresponding to an erroneous data block represented by the prescribed logic level of a bit included in the error control signal.

Claim 9

A signal transmission system using a selective automatic repeat request system which comprises a transmission section including first memory means for storing data being transmitted in the form having the prescribed block length measured by a number of bits, control means for selecting a data block having the prescribed serial number from among those which are stored in the memory means connected to the output of the control means, and means for attaching the prescribed check code to the selected data block and for transmitting the code attached data block to a communication channel; and a receiving section including means for receiving a data block delivered from the transmission section through the communication channel, error detection means for judging whether a data block supplied to the receiving section has an error, second memory means connected to the output of the detection means for successively storing only error-free correct data blocks included in those which are conducted to the receiving section, and means which distinguishes between an erroneous data block detected by the detection means and an error-free data block and which generates an error control signal including a negative acknowledgement information when an erroneous data block is detected and no control signal when no erroneous data block is detected, said error control signal indicating a demand for the transmission section to supply the receiving section with a new error-free data block corresponding to said erroneous data block and said error control signal being transmitted through the communication channel to the control means in the transmission section so that the control means selects the data block corresponding to the erroneous data block; and wherein the transmission section retransmits to the receiving section with an error-free data block corresponding to an erroneous data block represented by the prescribed logic level of a bit included in the error control signal.

Claim 10

The signal transmission system according to claim 7, wherein the error control signal is formed of a plurality of bits, each of which corresponds to one data block and does not contain an error correction check bit.

Claim 11

The signal transmission system according to claim 7, wherein the pattern error control signal-generating means includes a multiplexer circuit having data block receiving terminals and retransmission demand signal receiving terminals for producing one output signal for each data block received; 1 bit memories provided in the same number as the data blocks and further designed to store a bit having the prescribed logic level to denote an erroneous one of the respective data blocks; and a switching circuit connected between the output of 1-bit memories and the retransmission demand signal receiving terminals of the multiplexer for converting all outputs from said 1 bit memories into a pattern whose serially arranged bits represent the respective data blocks.