Data message control system

Claim 2

In a data handling device having a memory for storing data and input means for supplying data messages to the memory for subsequent transmission to a receiving station, a data message control system comprising: means for receiving at least one transmit signal subsequent to the storage of a data message in the memory, means for receiving from the receiving station a message acknowledgement signal indicating the successful transmission of the data message to the receiving station, means responsive to the initial transmit signal and the subsequent message acknowledgement signal for preventing input of data to said memory from said input means during the period of time between said initial transmit signal and said acknowledgement signal and permitting input of data to said memory from said input means during the period of time between said acknowledgement signal and the next initial transmit signal, means responsive to said initial transmit signal for transmitting predetermined identifying data to the receiving station and thereafter transmitting the data message stored in the memory to the receiving station and responsive to each subsequent transmit signal received prior to said acknowledgement signal for transmitting the same predetermined identifying data to the receiving station and thereafter transmitting the same data message stored in the memory to the receiving station, and means responsive to said message acknowledgement signal for changing said predetermined identifying data such that the next data message transmitted to the receiving station will be identified by different predetermined identifying data.

Claim 3

A data message control system as defined by claim 1 further comprising bi-stable circuit means for establishing predetermined identifying data such that predetermined identifying data in a first form is transmitted when said bi-stable circuit means is in its first stable state and predetermined identifying data in a second form is transmitted when said bi-stable circuit means is in its second stable state, said means for changing said predetermined identifying data comprising means shifting the state of said bi-stable circuit means in response to each message acknowledgement signal.

Claim 4

A data message control system as defined by claim 2 wherein sAid means for controlling input of data to the memory comprises: at least one memory input AND gate, a first input of said memory input AND gate communicating with the data input means for receiving data input signals therefrom and the output of said memory input AND gate communicating with the memory for supplying data input signals thereto, and bi-stable circuit means, means shifting said bi-stable circuit means to its first stable state in response to each initial transmit signal and means shifting said bi-stable circuit mean to its second stable state in response to the message acknowledgement signal following each initial transmit signal, a second input of said memory input AND gate communicating with said bi-stable circuit means such that transmission of data input signals to the memory is inhibited when said bi-stable circuit means is in its first stable state.

Claim 5

A data message control system as defined by claim 2 wherein said bi-stable circuit means for establishing predetermined identifying data has first and second input terminals and respective first and second output terminals, and wherein said data message control means further comprises: a first AND gate having an output connected to said first input terminal only of said bi-stable circuit means, and a second AND gate having an output connected to said second input terminal only of said bi-stable circuit means, said first AND gate having a first input connected to said second output terminal of said bi-stable circuit means, said second AND gate having a first input connected to said first output terminal of said bi-stable circuit means, and said first and second AND gates each having a second input connected to receive message acknowledgement signals from the receiving station, the feedback from said output terminals to said AND gates causing the state of said bi-stable circuit means to alternate in response to successive message acknowledgement signals.

Claim 6

A data message control system as defined by claim 1 further comprising: a first bi-stable circuit means, means alternating the state of said first bi-stable circuit means between first and second stable states in response to successive message acknowledgement signals, a second bi-stable circuit means, means shifting said second bi-stable circuit means to its first stable state in response to each transmit signal and means shifting said second bi-stable circuit means to its second stable state a predetermined period of time after each transmit signal, an AND gate having a first input communicating with said first bi-stable circuit means for receiving therefrom an indication of the state of said first bi-stable circuit means in the form of the presence or absence of a signal, the output of said AND gate communicating with the receiving station, a second input of said AND gate communicating with said second bi-stable circuit means such that transmission of signals to the receiving station is inhibited when said second bi-stable circuit means is in its second stable state, and at least one memory output AND gate, a first input of said memory output AND gate communicating with the memory for receiving data output signals therefrom and the output of said memory output AND gate communicating with the receiving station for supplying data output signals thereto, a second input of said memory output AND gate communicating with said second bi-stable circuit means such that transmission of data output signals to the receiving station is inhibited when said second bi-stable circuit means is in its first stable state, whereby a signal indicating the state of said first bi-stable circuit means and thereby serving as predetermined identifying data may be communicated to the receiving station when said second bi-stable circuit means is in its first stable state and the data message stored in the memory may be transmitted when said second bi-stable circuit means is in Its second stable state.

Claim 7

A data message control system as defined by claim 5 wherein said means for controlling input of data to the memory comprises: at least one memory input AND gate, a first input of said memory input AND gate communicating with the data input means for receiving data input signals therefrom and the output of said memory input AND gate communicating with the memory for supplying data input signals thereto, and a third bi-stable circuit means, means shifting said third bi-stable circuit means to its first stable state in response to each initial transmit signal and means shifting said third bi-stable circuit means to its second stable state in response to the message acknowledgement signal following each initial transmit signal, a second input of said memory input AND gate communicating with said third bi-stable circuit means such that transmission of data input signals to the memory is inhibited when said third bi-stable circuit means is in its first stable state.

Claim 8

A data message control system as defined by claim 1 further comprising: a first bi-stable circuit means having first and second input terminals and respective first and second output terminals, a first AND gate having an output connected to said first input terminal only of said first bi-stable circuit means, a second AND gate having an output connected to said second input terminal only of said first bi-stable circuit means, said first AND gate having a first input connected to said second output terminal of said first bi-stable circuit means, said second AND gate having a first input connected to said first output terminal of said first bi-stable circuit means, and said first and second AND gates each having a second input connected to receive message acknowledgement signals from the receiving station such that each message acknowledgement signal will be transmitted through one only of said first and second AND gates to shift the state of said first bi-stable circuit means, a second bi-stable circuit means having first and second input terminals and respective first and second output terminals, means for supplying transmit signals to said first input terminal of said second bi-stable circuit means to shift said second bi-stable circuit means to its first stable state and means responsive to transmit signals for supplying a signal to said second input terminal of said second bi-stable circuit means at a predetermined period of time after each transmit signal to shift said second bi-stable circuit means to its second stable state, a third AND gate having a first input connected to one of the output terminals of said first bi-stable circuit means for receiving therefrom an indication of the state of said first bi-stable circuit means in the form of the presence or absence of a signal, the output of said AND gate communicating with the receiving station, a second input of said third AND gate communicating with said first output terminal said second bi-stable circuit means such that transmission of signals to the receiving station is inhibited when said second bi-stable circuit means is in its second stable state, and at least one memory output AND gate, a first input of said memory output AND gate communicating with the memory for receiving data output signals therefrom and the output of said memory output AND gate communicating with the receiving station for supplying data output signals thereto, a second input of said memory output AND gate communicating with said second output terminal of said second bi-stable circuit means such that transmission of data output signals to the receiving station is inhibited when said second bi-stable circuit means is in its first stable state, whereby a signal indicating the state of said first bi-stable circuit means and thereby serving as predetermined identifying data may be communicated to the receiving station when said second bi-stable circuIt means is in its first stable state and the data message stored in the memory may be transmitted when said second bi-stable circuit means is in its second stable state.

Claim 9

A data message control system as defined by claim 7 further comprising means for generating a cyclic sequence of regular counting signals, said memory output AND gate having a third input connected to said counting signal generating means for receiving therefrom a unique one of the counting signals, and said third AND gate having a third input connected to said counting signal generating means for receiving therefrom a predetermined one of the counting signals.

Claim 10

A data message control system as defined by claim 8 further comprising means responsive to transmit signals for starting said counting signal generating means, said second input terminal of said second bi-stable circuit means being connected to said counting signal generating means so as to receive therefrom a predetermined one only of the counting signals, said second bi-stable circuit shifting to its second stable state upon receipt of the first such signal, said predetermined counting signal supplied to said third AND gate being earlier in the sequence of counting signals than said predetermined counting signal supplied to said second input terminal of said second bi-stable circuit means so that the indication of the state of said first bi-stable circuit means is communicated to the receiving station before said second bi-stable circuit is shifted to its second state.

Claim 11

A data message control system as defined by claim 9 wherein said means for controlling input of data to the memory comprises: at least one memory input AND gate, a first input of said memory input AND gate communicating with the data input means for receiving data input signals therefrom and the output of said memory input AND gate communicating with the memory for supplying data input signals thereto, and a third bi-stable circuit means, means shifting said third bi-stable circuit means to its first stable state in response to each initial transmit signal and means shifting said third bi-stable circuit to its second stable state in response to the message acknowledgement signal following each initial transmit signal, a second input of said memory input AND gate communicating with said third bi-stable circuit means such that transmission of data input signals to the memory is inhibited when said third bi-stable circuit is in its first stable state.

Claim 12

A data message control system as defined by claim 10 wherein said first and second AND gates each have a third input connected to said third bi-stable circuit means such that only a first message acknowledgement signal following one or more transmit signals is transmitted to said first bi-stable circuit means, thereby assuring that successive data messages will be identified by different predetermined identifying signals.

Claim 13

A data message control system as defined by claim 11 further comprising manually operable means for supplying a transmit signal to said second and third bi-stable circuit means and said means for starting said counting signal generating means.

Claim 14

A data message control system as defined by claim 12 further comprising means for receiving from the receiving station a signal indicating the unsuccessful transmission of the data message and supplying the signal as a transmit signal to said second and third bi-stable circuit means and said means for starting said counting signal generating means.

Claim 15

A data message control system as defined by claim 13 wherein said means for starting said counting signal generating means includes a fourth bi-stable circuit means.