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US3388378A Expired / Lapsed US ⏱️ 0.0 years remaining

Error detection and correction apparatus for duplex communication system

Assignee: Western Union Telegraph Co
•
Filing: 1964-09-22
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Granted: 1968-06-11
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Expires: 1984-09-22
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Abstract

Abstract 1,100,037. Data transmission systems. INTERNATIONAL STANDARD ELECTRIC CORPORATION. 17 Sept., 1965 [22 Sept., 1964], No. 39738/65. Heading H4P. In a duplex system, data is sent in blocks comprising accept/reject bits followed by information bits, and then check bits, the former indicating whether or not the last block received contained an error. Reception of reject bits causes repetition of the faulty block. In the system described alternate blocks A and B are sent from the master station. Successive groups of characters read from a tape are passed to alternate stores A and B. A check word is calculated for each group by weighting the information bits and adding. At the slave receiver the block is stored in the appropriate block store. The check word is derived and compared with the received check word. If no error is indicated the stored block is passed to a teleprinter and an accept signal is added to the next block transmitted from the slave. The teleprinter is now switched to accept bits from the other store. If the master station detects an accept signal it erases the relevant store, e.g. A, which is then refilled from the tape. If a reject signal is received it completes transmission of the current block B but sends a mutilated check word. Store A is not erased and block A is now repeated. Block B, with its mutilated check word, and block A are repeated until an accept signal is received for block A. If the slave station had sent an accept signal which was received as a reject signal at the master due to mutilation, the same repetition procedure would ensue, but the repeated block A would not be passed to the teleprinter because reception of the previous block A would have switched the teleprinter to respond only to block B signals. Two synchronous bits preceding each block are used to synchronize the receiver clock by the addition and deletion of feed-back loops in a counter divider, Fig. 9E (not shown).

Inventors

  • 👤 Steeneck Robert
  • 👤 John R Cowan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 14:57
CPC Classifications
H; H04; H04L; H04L69/00; H04L69/30; H04L69/32; H04L69/322; H04L69/324; H04L1/00; H04L1/12; H04L1/16; H04L1/18

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

US2805278A Cited
US3001017A Cited
US2985714A Cited
US3208049A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1971-06-11 1971-12-11 1972-06-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1975-06-11 1975-12-11 1976-06-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1979-06-11 1979-12-11 1980-06-11 $7700.00 Window Closed / Lapsed

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